User`s manual

BL160060 s System Development
STAT0 (04H)
76543210
RDRF OVRN PE FE RIE /DCD0 TDRE TIE
RRRRR / WRRR / W
STAT1 (05H)
76543210
RDRF OVRN PE FE RIE CTS1E TDRE TIE
RRRRR / WRRR / W
Asynchronous Serial Communication Interface
(ASCI)
The Z180 incorporates an ASCI interface that supports two independent
full-duplex channels.
ASCI Status Registers
A status register for each channel provides information about the state of
each channel and allows interrupts to be enabled and disabled.
/DCD0 (Data Carrier Detect)
This bit echoes the state of the /DCD0 input pin for Channel 0. However,
when the input to the pin switches from high to low, the data bit switches
low only after STAT0 has been read. The receiver is held reset as long as
the input pin is held high. This function is not generally useful because an
interrupt is requested as long as /DCD0 is a 1. This forces the programmer
to disable the receiver interrupts to avoid endless interrupts. A better
design would cause an interrupt only when the state of the pin changes. In
the BL1600, this pin is tied to ground.
TIE (Transmitter Interrupt Enable)
This bit masks the transmitter interrupt. If set to 1, an interrupt is re-
quested whenever TDRE is 1. The interrupt is not edge-triggered. Set this
bit to 0 to stop sending. Otherwise, interrupts will be requested continu-
ously as soon as the transmitter data register is empty.
TDRE (Transmitter Data Register Empty)
A 1 means that the channel is ready to accept another character. A high
level on the /CTS pin forces this bit to 0 even though the transmitter is
ready.