User`s manual

BL1600 Power Management s 127
Power Failure Management
Figure H-1 shows the power-failure detection circuitry of the BL1600.
Figure H-1. BL1600 Power-Failure Detection Circuit
Power Failure Sequence
The following events occur as the input power fails.
1. The ADM691 first triggers a power-failure /NMI (nonmaskable
interrupt) when the unregulated DC input voltage falls below approxi-
mately 7.9 V (as determined by the voltage divider R1R2), allowing
the power-failure routine to store important state data during the
holdup interval, t
H
.
2. At some point, the raw input voltage level will drop below the regulat-
ed voltage level required by the regulators dropout voltage, whereupon
the regulated output will begin to droop. The ADM691 next triggers a
system reset, /RESET, when the regulated +5V supply falls below
≈4.65 V. The ADM691 forces the chip-enable line of the SRAM high
(standby mode). Thus your power-failure routine uses the holdup
interval (the time between steps 1 and 2), t
H
, to store important state
data.
3. The SRAM switches to the backup battery when the regulated voltage
falls below the batterys voltage, preserving the RAMs data.
4. The ADM691 keeps /RESET enabled until the regulated voltage drops
below 1 V. At this point the ADM691 ceases operating. By this time,
the portion of the circuitry not battery-backed should have long since
ceased functioning.
PFI
/PFO
/NMI
DCIN
R1
R2
IC691
Z180
/RES
/RESET
Data
Bus
D6
U13
U15
VBAT
VBAT