User`s manual

BL1600120 s Memory, I/O Map, and Interrupt Vectors
Table G-5. Other I/O Addresses (concluded)
Address Name Data Bits Description
0x127 SCL D0
EEPROM clock bit. Set the clock high
by setting bit 0 of this address, and low
by clearing bit 0.
0x130 OUTBYTE D0–D7
8-bit parallel TTL-level digital output
(OUTB1–OUTB8 on the schematic).
0x150 USER1 — Base address of expansion register
group 1. These 16 registers have ad-
dresses 0x150 to 0x15F. Addressing
any of these registers makes /USER1
assert.
0x160 USER2 — Base address of expansion register
group 2. These 16 registers have ad-
dresses 0x160 to 0x16F. Addressing
any of these registers makes /USER2
assert.
0x170 USER3 — Base address of expansion register
group 3. These 16 registers have ad-
dresses 0x170 to 0x17F. Addressing
any of these registers makes /USER3
assert.
0x1C0 WDOG — Watchdog is “hit” (J1:27-28 enables
watchdog) by reading or writing this
address.