User`s manual
BL1600114 s Memory, I/O Map, and Interrupt Vectors
Table G-1. Memory Access Times
(ns)
Clock Frequency EPROM SRAM
9.216 MHz, 0 wait states 122 176
9.216 MHz, 1 wait state 230 283
T
w
T1 T2
A0A15
/IOE
/RD
/WR
T3
T
w
1
D0D7 write
D0D7 read
The standard memory cycles require an access time of 2.5T - 95 nanosec-
onds. Table G-1 lists the memory access times required for various clock
frequencies and wait states.
The memory access times in Table G-1 were calculated assuming that LIR
cycles only take place in EPROM. These access times are conservative,
and no problem should be encountered by using an EPROM with a
memory access time that is more than the time listed in Table G-1.
Input/Output Cycle Timing
Customer peripheral devices are usually interfaced as I/O devices. This is
convenient because only eight address lines need to be decoded in most
cases. Figure G-4 shows how wait cycles are inserted in I/O cycles. At
least one wait cycle (T
W
) is always inserted. Up to four additional wait
states can be inserted, depending on the setup of the wait-state generator.
One additional wait state, the default number (T
W1
), is shown in Figure G-4.
Figure G-4. Inserting Wait Cycles in I/O Cycles