User`s manual

BL1600 Memory, I/O Map, and Interrupt Vectors s 113
Memory and Input/Output Cycle Timing
There are two types of memory cycles that need to be considered: standard
memory cycles and Load Instruction Register (LIR) cycles. LIR cycles,
which fetch the op code, have the most critical timing requirement. The
memory access time, t, in nanoseconds, can be calculated for these cycles
using
t = 2T - 95 , (G-1)
where T is the period of a clock cycle. Figure G-3 shows these cycles with
and without a wait state.
Figure G-3. Memory Cycles for 9.216 MHz Processor
With and Without a Wait State
The standard version of the PAL generates a wait state only during the LIR
cycles. Therefore it is called a ½ wait state PAL.
T1 T2 TwT3
address
T1 T2 T3
address
data data
T
AD
= 70 ns T
AD
= 70 nsT
DRS
= 25 ns T
DRS
= 25 ns
0 wait states 1 wait state
/ME
/RD
/WR
0 wait access time = 2T - 95 ns 1 wait access time = 3T - 95 ns
= 122 ns for 9.216 MHz clock = 230 ns for 9.216 MHz clock