User`s manual
XP8000 Series (PLCBus
TM
)
Z-World 530-757-3737 3
First byte Mode Addresses Full address encoding
1 ––––0000 4 bits x 3 256 0000 xxxx xxxx
2 ––––0001 256 0001 xxxx xxxx
3 ––––0010 256 0010 xxxx xxxx
4 ––––0011 256 0011 xxxx xxxx
5 –––x0100 5 bits x 3 2,048 x0100 xxxxx xxxxx
7 –––x0101 2,048 x0101 xxxxx xxxxx
7 –––x0110 2,048 x0110 xxxxx xxxxx
8 –––x0111 2,048 x0111 xxxxx xxxxx
9 ––xx1000 6 bits x 3 16,384 xx1000 xxxxxx xxxxxx
10 ––xx1001 16,384 xx1001 xxxxxx xxxxxx
11 ––xx1010 6 bits x 1 4 xx1010
12 ––––1011 4 bits x 1 1 1011 (expansion reg.)
13 xxxx1100 8 bits x 2 4,096 xxxx1100 xxxxxxxx
14 xxxx1101 8 bits x 3 1 Meg xxxx1101 xxxxxxxx xxxxxxxx
15 xxxx1110 8 bits x 1 16 xxxx1110
16 xxxx1111 8 bits x 1 16 xxxx1111
The mode notation indicates how many bus address cycles must take place
and how many bits are placed on the bus each cycle. For example, “5 bits x
3” means 3 bus cycles and 5 address bits each time.
Primitive functions are available in Z-World’s software libraries
to carry out these bus cycles. Higher level functions are also
available. They take care of the details for you.
Bus Addresses
To allow you to use an arbitrary combination of bus devices, in
anticipation of future products and third-party products,
Z-World has established a two-level addressing scheme. The
first level in the scheme specifies how addresses are encoded
when placed on the bus. The second level in the scheme speci-
fies the actual addresses assigned to Z-World devices.
First level: placing addresses on the bus
You place an address on the bus by writing to BUSADR0,
BUSADR1 and BUSADR2 in succession. Doing so places ad-
dress bits on the data lines (D0X–D7X) and modifies the mode
lines (A3X–A1X). A PLCBus devices must respond by compar-
ing the address bits with its own address.
The lower four bits of the first address byte identify address
categories. There are 16 address categories, given in the table
below. The symbol “–” indicates an unused bit. An “x” indi-
cates the address bit may be a 1 or a 0. Each PLCBus device
recognizes its own category and responds to that and no other.
The ‘x’ bits are further encoded by the second level of the ad-
dressing scheme, as you will see later.
Not all these categories are in use.
Z-World software also maintains “logical” address spaces that
map to physical address spaces. Generally, the logical space
simply numbers the boards sequentially.
Abbreviated Addresses
Assume you have just placed a full PLCBus address on the bus
and wish to place another address on the bus. If the first two
bytes of the next address are the same as for the previous ad-
dress, it is sufficient to write BUSADR2 only.
Expansion Register
Addressing the expansion register is a special case: the encod-
ing scheme uses one byte which has a fixed value (0xB). When
you write to this address, all devices which have an expansion
register respond by latching the data from the next BUSWR.
The following sample code writes 3 to expansion registers:
ld a,0xB ;0xB addresses ALL exp regs
out0 (BUSADR0),a
ld a,3 ;All expansion registers get 3
out0 (BUSWR),a
...
At present, no Z-World device has an expansion register. If you
design a PLCBus expansion card, the use of an expansion regis-
ter is up to you.
Second Level: Physical Device Addresses
The second level of the addressing scheme specifies what ad-
dresses a PLCBus device can occupy. This applies primarily to
PLCBus devices manufactured by Z-World.
Each Z-World expansion card has a unique second-level address
based on PAL coding and jumper wiring. The second-level ad-
dress scheme is described, for each product, in the section that
describes the product.
For PLCBus devices that have PAL encodings, you will have to
order boards with the specific PAL in the quantity you need, if
you want to have more than one such board on a PLCBus.
Building Your Own
PLCBus expansion devices must be designed ac-
cording to the following rules:
1 The device must have two 26-pin headers that
match the PLCBus signals and operate accord-
ing to those signals.
2 The device must not rely on critical timing,
such as a minimum delay between successive
register accesses.
3 The device must be capable of being selected
and deselected at any time without adverse ef-
fect.
4 The device must operate according to the first
level addressing rules given here. They do not
have to operate according to the second level
rules given next, but must not interfere with
devices that do.