User`s manual

PK2100
Appendix D: I/O Map and Interrupt Vectors s D-3
Table D-1. Addresses 00-3F for Z180 Internal I/O Registers (concluded)
Address Name Description
23 DAR0L DMA Destination Address, Channel 0, least
24 DAR0H DMA Destination Address, Channel 0, most
25 DAR0B
DMA Destination Address, Channel 0,
extra bits
26 BCR0L DMA Byte Count Register, Channel 0, least
27 BCR0H DMA Byte Count Register, Channel 0, most
28 MAR1L DMA Memory Address Register, Channel
1, least
29 MAR1H DMA Memory Address Register, Channel
1, most
2A MAR1B
DMA Memory Address Register, Channel
1, extra bits
2B IAR1L
DMA I/O Address Register, Channel 1,
least
2C IAR1H
DMA I/O Address Register, Channel 1,
most
2D — Reserved
2E BCR1L DMA Byte Count Register, Channel 1, least
2F BCR1H DMA Byte Count Register, Channel 1, most
30 DSTAT DMA Status Register
31 DMODE DMA Mode Register
32 DCNTL DMA/WAIT Control Register
33 IL Interrupt Vector Low Register
34 ITC Interrupt/Trap Control Register
35 — Reserved
36 RCR Refresh Control Register
37 — Reserved
38 CBR MMU Common Base Register
39 BBR MMU Bank Base Register
3A CBAR MMU Common/Bank Area Register
3B–3D — Reserved
3E OMCR Operation Mode Control Register
3F ICR I/O Control Register