User`s manual

PK2100
D-2 s Appendix D: I/O Map and Interrupt Vectors
I/O Map
The internal registers for the input/ouput devices built into to the Z180
processor occupy the first 40 (hex) addresses of the input/output space.
Table D-1 lists the addresses of these internal registers.
Table D-1. Addresses 00-3F for Z180 Internal I/O Registers
Address Name Description
00 CNTLA0 Control Register A, Serial Channel 0
01 CNTLA1 Control Register A, Serial Channel 1
02 CNTLB0 Control Register B, Serial Channel 0
03 CNTLB1 Control Register B, Serial Channel 1
04 STAT0 Status Register, Serial Channel 0
05 STAT1 Status Register, Serial Channel 1
06 TDR0 Transmit Data Register, Serial Channel 0
07 TDR1 Transmit Data Register, Serial Channel 1
08 RDR0 Receive Data Register, Serial Channel 0
09 RDR1 Receive Data Register, Serial Channel 1
0A CNTR Clocked Serial Control Register
0B TRDR Clocked Serial Data Register
0C TMDR0L Timer Data Register, Channel 0, least
0D TMDR0H Timer Data Register, Channel 0, most
0E RLDR0L Timer Reload Register, Channel 0, least
0F RLDR0H Timer Reload Register, Channel 0, most
10 TCR Timer Control Register
11–13 — Reserved
14 TMDR1L Timer Data Register, Channel 1, least
15 TMDR1H Timer Data Register, Channel 1, most
16 RLDR1L Timer Reload Register, Channel 1, least
17 RLDR1H Timer Reload Register, Channel 1, most
18 FRC Free-Running Counter
19–1F — Reserved
20 SAR0L DMA Source Address, Channel 0, least
21 SAR0H DMA Source Address, Channel 0, most
22 SAR0B DMA Source Address, Channel 0, extra bits
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