User`s manual

PK2200D-90 s Interrupts and Adresses
Table D-4. Z180 Internal I/O Device Registers (concluded)
Address Name Description
0x21 SAR0H DMA Source Address, Channel 0, high
0x22 SAR0B DMA Source Address, Channel 0, extra bits
0x23 DAR0L DMA Destination Address, Channel 0, low
0x24 DAR0H DMA Destination Address, Channel 0, most
0x25 DAR0B Destination Address, Channel 0, extra bits
0x26 BCR0L DMA Byte Count Register, Channel 0, low
0x27 BCR0H DMA Byte Count Register, Channel 0, high
0x28 MAR1L DMA Memory Address Register, Channel 1,
low
0x29 MAR1H
DMA Memory Address Register, Channel 1,
high
0x2A MAR1B DMA Memory Address Register, Channel 1,
extra bits
0x2B IAR1L DMA I/O Address Register, Channel 1, low
0x2C IAR1H DMA I/O Address Register, Channel 1, high
0x2D — Reserved
0x2E BCR1L DMA Byte Count Register, Channel 1, low
0x2F BCR1H DMA Byte Count Register, Channel 1, high
0x30 DSTAT DMA Status Register
0x31 DMODE DMA Mode Register
0x32 DCNTL DMA/WAIT Control Register
0x33 IL Interrupt Vector Low Register
0x34 ITC Interrupt/Trap Control Register
0x35 — Reserved
0x36 RCR Refresh Control Register
0x37 — Reserved
0x38 CBR MMU Common Base Register
0x39 BBR MMU Bank Base Register
0x3A CBAR MMU Common/Bank Area Register
0x3B–3D — Reserved
0x3E OMCR Operation Mode Control Register
0x3F ICR I/O Control Register