User`s manual

XP8500 and Exp-A/D12
80 s PLCBus
Z-World provides software drivers that access the PLCBus. To allow
access to bus devices in a multiprocessing environment, the expansion
register and the address registers are shadowed with memory locations
known as shadow registers. The 4-byte shadow registers, which are saved
at predefined memory addresses, are as follows.
SHBUS1 SHBUS1+1
SHBUS0 SHBUS0+1 SHBUS0+2 SHBUS0+3
Bus expansion BUSADR0 BUSADR1 BUSADR2
Before the new addresses or expansion register values are output to the
bus, their values are stored in the shadow registers. All interrupts that use
the bus save the four shadow registers on the stack. Then, when exiting the
interrupt routine, they restore the shadow registers and output the three
address registers and the expansion registers to the bus. This allows an
interrupt routine to access the bus without disturbing the activity of a
background routine that also accesses the bus.
To work reliably, bus devices must be designed according to the following
rules.
1. The device must not rely on critical timing such as a minimum delay
between two successive register accesses.
2. The device must be capable of being selected and deselected without
adversely affecting the internal operation of the controller.
Allocation of Devices on the Bus
4-Bit Devices
Table A-4 provides the address allocations for the registers of 4-bit
devices.
Table A-4. Allocation of Registers
A1
A2 A3 Meaning
000j 000j xxxj
digital output registers, 64 registers
64 × 8 = 512 1-bit registers
000j 001j xxxj analog output modules, 64 registers
000j 01xj xxxj
digital input registers, 128 registers
128 × 4 = 512 input bits
000j 10xj xxxj analog input modules, 128 registers
000j 11xj xxxj 128 spare registers (customer)
001j xxxj xxxj 512 spare registers (Z-World)
j controlled by board jumper
x controlled by PAL