Service manual

Appendix C Functional Description C-25
C.1.15.5 FEPS
The fast Ethernet parallel port (FEPS) ASIC provides throughput for I/O devices
connected to the Ethernet, SCSI, and parallel port interfaces. The FEPS ASIC consists
of a frame buffer controller ASIC and a RAMDAC ASIC.
The FEPS ASIC:
■ Integrates 20-Mbyte per second SCSI interface core with low system overhead
■ Integrates 10-Mbit per second and 100-Mbit per second Ethernet
■ Complies with IEEE 1496 SBus specification. Also provides for 64-bit SBus
transfers
■ Supports SBus extended transfer and 64-byte burst transfer
■ Provides 25-MHz SBus operation
FBC
The frame buffer controller (FBC) ASIC is the graphics draw ASIC that interfaces to
the UPA and to the UPA graphics FBRAM. The FBC ASIC provides graphics draw
acceleration.
The FBC ASIC:
■ Includes a UPA slave device with write-mostly philosophy
■ Supports single-buffered and double-buffered with Z buffer configurations
■ Interfaces with 3DRAM to achieve accelerated graphics performance
■ Supports frame buffer to frame buffer copy
■ Supports viewport clipping, picking, and pixel processing
■ Supports byte, plane masks, raster operations, blend operations, and conditional
writes in 3DRAM
RAMDAC
The RAM digital-to-analog converter (RAMDAC) ASIC is listed for reference. It is
being designed in conjunction with an outside vendor.
The RAMDAC ASIC includes:
■ Built-in VTG
■ Direct interface to FBRAMs
■ On-board phase-lock loop (PLL) and clock generator circuitry for the pixel clock
■ 64 X 64 cursor LUT
■ Direct support for X visual types