Service manual

C-24 Sun Ultra 2 Series Service Manual • July 1996
C.1.15.2 SYSIO
The system I/O controller (SYSIO) ASIC bridges between the UPA and the SBus.
The SYSIO ASIC:
■ Contains the IOMMU
■ Integrates streaming buffer to enhance sequential I/O performance
■ Provides logic for dispatching interrupt vectors to processors
■ Provides ECC generation and checking logic
C.1.15.3 BMX
The buffered memory crossbar (BMX) ASIC is a three-port crossbar connecting one
144-bit UPA data bus, one 288-bit-wide DRAM memory bus, and one 72-bit UPA
data bus. To maintain a manageable pin count, the devices are sliced so that 18 BMX
ASICs are needed to form the complete switch function.
The BMX ASIC includes:
■ 8 bits of UPA 128, 4 bits of UPA 72, and 16 bits of DRAM bus per ASIC
■ Switch connections controlled by SC
C.1.15.4 RISC
This reset, interrupt, scan, and clock (RISC) ASIC implements four functions: reset,
interrupt, scan, and clock. Generation and stretching of the reset pulse is performed
in this ASIC. Interrupt logic concentrates 42 different interrupt sources into a 6-bit
code which communicates with the SYSIO ASIC. The RISC ASIC also integrates a
JTAG controller. In cases where there are multiple processors, they are required to
run at the same frequency. A 3-bit code is output by each processor module to
indicate the speed for that module. Logic inside the RISC ASIC determines the
minimum value of the processor codes, and outputs the selected value for the
remaining clock logic to set the main system frequency.
The RISC ASIC:
■ Determines system clock frequency
■ Controls reset generation
■ Provides JTAG
■ Performs SBus and miscellaneous interrupt concentration for SYSIO
■ Controls flash PROM programming, frequency margining, and lab console
operation
■ 25-MHz operation