Service manual

Appendix C Functional Description C-23
The following table lists each ASIC by name and provides characteristics of each
device.
C.1.15.1 SC_MP
The multiprocessing system controller (SC_MP) ASIC is the key element for
controlling the UPA and main memory. The SC_MP ASIC controls accesses from
UPA master device to UPA slave device, and UPA accesses to memory. SC_MP
includes a complete coherency controller which controls system dual tags (DTAGs).
The SC_MP ASIC:
■ Integrates memory controller functionality. Memory controller is programmable
to accommodate multiple DRAM and UPA speeds
■ Supports four groups of memory, each with four DSIMMs
■ Supports 16-Mbyte, 32-Mbyte, 64-Mbyte, and 128-Mbyte, 60-ns DSIMMs
■ Supports maximum memory configurations of 2 Gbytes with sixteen 128-Mbyte
DSIMMs
■ Supports three UPA masters and one UPA slave with independent address busses
(independent busses are required for graphics streaming)
■ Controls the BMX ASIC which connects the UPA data bus and memory
■ Controls the CBT ASICs
TABLE C-5 ASIC Characteristics
ASIC Name Gates RAM (bits) Package
Die Size (mm x
mm)
Power
(W)
Reqd Per
Unit
SC_MP 140K 0 372BGA 3.9 1
SYSIO 116K 14K 372BGA 10 x 10 2.7 1
BMX 7K 0 44TSSOP NA 0.2 18
RISC 7k 0 160MQFP 6.25 x 6.25 0.4 1
FBC 202K 16K RAM,
32K ROM
313BGA 10.54 x 10.54 5.9 1
CBT 0.4K 0 56TSSOP NA 0.2 18
RAMDAC 208PQFP NA 2.0 1
FEPS 115K 4K 240PQFP 2.0 1