Service manual

Appendix C Functional Description C-3
C.1.1 UPA
The UPA is a cache-coherent processor-to-memory interconnect. A key advantage of
the UPA processor-to-memory interconnect is a scalable bandwidth through the
support of multiple bussed interconnects for both data and address. Other
advantages include more bandwidth, high-performance graphics support with
two-cycle, single-word writes on the 64-bit UPA data bus, and centralized coherence
and memory controller functions (see
FIGURE C-1). The UPA consists of the following,
as implemented on the motherboard:
Eighteen buffered memory crossbar (BMX) ASICs and eighteen memory data
multiplexer-demultiplexer (CBT) ASICs
The BMX ASICs connect the 144-bit UPA processor data bus to a 576-bit
memory data bus through CBT ASICs, a 72-bit UPA data bus for graphics and
I/O devices
The memory path is 576 bits using 18 CBT ASICs
The processor(s) share(s) a UPA address bus (ADRSBUS1) with the SYSIO ASIC; a
second address bus (ADRSBUS0) supports slave UPA connection to the expansion
slot for graphics capability
Low voltage transistor-transistor logic (TTL) voltage levels for signal input
Low voltage complementary metal-oxide semiconductor (CMOS) voltage levels
for signal output
UPA performance characteristics includea peak bandwidth of 1.3-Gbytes per second
with one 144-bit processor data bus on an 83-MHz UPA.
C.1.2 SBus
The system unit or server uses the IEEE 1496 SBus (see FIGURE C-1). This includes:
16.6-MHz to 25-MHz operation. Default frequency is 25 MHz
Note SBus frequency is independent of processor and UPA operating frequencies.
Extended transfer mode (64-bit data path)
Transfer sizes to 64 bytes (maximum)
Parity
Dedicated interrupts for each SBus slot.
The system unit or server supports four SBus slots. The four slots are configured in
a side-by-side stacked configuration.