System information

Chapter 1. Introduction to LPAR on IBM System i5 9
If there are three processors in the System i5 system unit, with all three processors in the
shared processors pool, if a logical partition is allocated 0.8 processing units, then the logical
partition will have 8 milliseconds of processing time from 30 milliseconds of processing time.
For every 10 millisecond time slot, you give 8 milliseconds out of 30 milliseconds of
processing time available.
Figure 1-5 illustrates the processing time assignment from the shared processors pool to a
logical partition. The same condition applies for a logical partition with 1.5 processing units.
The logical partition will have 15 milliseconds of processing time available out of 30
milliseconds of processing time every 10 millisecond time slot. However, this logical partition
needs 2 virtual processors in the shared processors pool.
Figure 1-5 Processing time for logical partition with 0.8 processing units
Once the logical partition has used its processing time in every 10 millisecond time slot, it has
to wait for next the available processing time in the next 10 millisecond physical time slot.
For a dedicated logical partition, the processing time available for that partition is equal to a
number of physical processors assigned multiplied by 10 milliseconds. A logical partition with
a dedicated processor has better processing time utilization than a shared logical partition.
For capped logical partitions, it cannot exceed the processing time assigned to them. For
uncapped logical partitions, it is possible to use idle processing time in the shared processors
pool.
Before a processor can run a job, it must first get the data from DASD to main storage/
memory. The data from memory is then transferred into the cache memory. The data in the
cache memory is available to use by the processor. The process of moving data from DASD
into the memory is slower than reading data from cache memory, so it will take a longer time
to load data from DASD to cache for the first time. Frequently accessed data will remain in the
cache or memory in order to maintain fast data access. Figure 1-6 below illustrates the basic
flow of data loaded from DASD into memory, then into the cache memory, before being used
by the processor.
VP 1
VP 2
VP 3
10 ms
8 ms
VP 1
VP 2
VP 3
10 ms
8 ms
CPU cycle CPU cycle
Logical partition with 0.8 processing units
VP 1
VP 2
VP 3
10 ms
8 ms
VP 1
VP 2
VP 3
10 ms
8 ms
CPU cycle CPU cycle
Logical partition with 0.8 processing units