TI Extensa 61X Series (AcerNote 370P) Notebook Service Guide PART NO.: 2238309-0809 DOC. NO.
Copyright Copyright © 1997 by Acer Incorporated. All rights reserved. No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise, without the prior written permission of Acer Incorporated.
About this Manual Purpose This service guide contains reference information for the Extensa 610 notebook computer. It gives the system and peripheral specifications, shows how to identify and solve system problems and explains the procedure for removing and replacing system components. It also gives information for ordering spare parts.
Appendix E BIOS POST Checkpoints This appendix lists all the BIOS POST checkpoints. Appendix F Technical Bulletins and Updates This appendix reserves a space for technical bulletins and future updates. Appendix G Forms This appendix contains standard forms that can help improve customer service. Related product information AcerNote 370P User's Manual contains system description and general operating instructions. M1521, M1523 and M7101 Data Sheets contain information on the Acer chips.
Conventions The following are the conventions used in this manual: Text entered by user Screen messages Represents text input by the user. Denotes actual messages that appear onscreen. NOTE Gives bits and pieces of additional information related to the current topic. WARNING Alerts you to any damage that might result from doing or not doing specific actions. CAUTION Gives precautionary measures to avoid possible hardware or software problems.
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Table of Contents Chapter 1 1.1 1.2 System Introduction Overview.......................................................................................................................... 1-1 1.1.1 Features ........................................................................................................... 1-2 1.1.2 Rear Ports ........................................................................................................ 1-3 1.1.3 Indicator Light ......................................
1.4.17 Keyboard........................................................................................................1-23 1.4.17.1 1.5 1.4.18 FDD ...............................................................................................................1-24 1.4.19 HDD...............................................................................................................1-24 1.4.20 CD-ROM.....................................................................................................
2.4 2.5 2.6 2.7 2.8 2.9 ALI M7101 (Power Management Unit) .......................................................................... 2-24 2.4.1 Features ......................................................................................................... 2-24 2.4.2 Pin Diagram................................................................................................... 2-25 2.4.3 Pin Description .............................................................................................
2.10 2.11 2.12 2.9.5 Pin Diagram ...................................................................................................2-94 2.9.6 Pin Description...............................................................................................2-95 2.9.7 Functions Description.....................................................................................2-96 Charge Function ..........................................................................2-96 2.9.7.2 Discharge Function......
3.4 3.5 System Security................................................................................................................ 3-6 3.4.1 Floppy Disk Drive Control ............................................................................... 3-6 3.4.2 Hard Disk Drive Control .................................................................................. 3-6 3.4.3 System Boot Drive Control............................................................................... 3-7 3.4.
4.5 4.6 Disassembling the Inside Frame Assembly .....................................................................4-10 4.5.1 Removing the Heat Sink Assembly .................................................................4-10 4.5.2 Removing the Internal Drive ..........................................................................4-11 4.5.3 Replacing the CPU .........................................................................................4-12 4.5.4 Removing the Display ...............
List of Figures 1-1 Notebook.......................................................................................................................... 1-1 1-2 Rear Ports ........................................................................................................................ 1-3 1-3 Indicator Light ................................................................................................................. 1-4 1-4 Main Board Layout (Top Side) .......................................
xiv 2-14 PCI-to-CardBus terminal assignments ............................................................................2-62 2-15 NS87336VJG Block Diagram .........................................................................................2-77 2-16 NS87336VJG Pin Diagram.............................................................................................2-78 2-17 YMF715 Block Diagram ................................................................................................
4-20 Removing the Battery Connector Board.......................................................................... 4-18 4-21 Unplugging the LCD Cover Switch and Speaker Cables................................................. 4-18 4-22 Removing the Charger Board ......................................................................................... 4-19 4-23 Detaching the Motherboard from the Inside Assembly Frame......................................... 4-19 4-24 Removing the PC Card Slot Unit..
List of Tables xvi 1-1 Port Descriptions .............................................................................................................1-3 1-2 Indicator Status Descriptions ............................................................................................1-4 1-3 System Specifications .......................................................................................................1-5 1-3 System Specifications (continued).................................................
1-28 CD-ROM Specifications................................................................................................. 1-25 1-29 Battery Specifications..................................................................................................... 1-25 1-30 Charger Specifications ................................................................................................... 1-26 1-31 DC-DC Converter Specifications..........................................................................
2-14 NS87336VJG Pin Descriptions .......................................................................................2-79 2-15 YMF715 Descriptions.....................................................................................................2-89 2-16 T62.062.C Absolute Maximum Ratings Table ................................................................2-92 2-17 T62.062.C Electrical Characteristics Table .....................................................................2-92 2-18 T62.
C h a p t e r 1 System Introduction This chapter introduces the notebook, its features, components and specifications. 1.1 Overview The notebook was designed with the user in mind. The figure below shows the notebook with the display open.
1.1.1 Features Here are just a few of the notebook’s many features: Performance • High-end Pentium microprocessor • Support 64-bit main memory and external (L2) cache memory • Large LCD display (DualScan STN and TFT active matrix.) • PCI local bus video with graphics acceleration and 1MB video RAM boost video performance • Internal 3.
1.1.2 1 2 3 4 5 Rear Ports DC-in Port Microphone-in Port Line-in Port Line-out Port External Floppy Drive Connector 6 7 8 9 Serial Port Parallel Port External CRT Port PS/2 Port Figure 1-2 Rear Ports The following table describes these ports. Table 1-1 Port Descriptions # Icon Port Connects to... 1 DC-in Port AC adapter and power outlet 2 Microphone-in Port External 3.5mm minijack condenser microphone 3 Line-in Port Line-in device (e.g.
Indicator Light Indicator Light Figure 1-3 Indicator Light This two-way indicator light allows you to see the notebook status when the display is open or closed. The indicator serves both as a power and battery-charging indicator. See Table 1-2. Table 1-2 Indicator Status Descriptions Indicator Status Power Switch Condition Green On Charged battery is installed or a power AC adapter is connected to the notebook.
1.1.4 System Specifications Overview Table 1-3 System Specifications Item Standard Optional Microprocessor Intel Pentium™ processor (Intel P54CSLM 120/133/150 MHz) Intel P55CLM - 133/150 with MMX System memory 8MB / 16MB Dual 64-bit memory banks Expandable to 64MB using 8, 16 and 32MB soDIMMs Flash ROM BIOS 256KB Data storage devices Removable 12.5mm, 2.5-inch, 1.0GB Enhanced-IDE hard disk 1+GB Enhanced-IDE hard disk drive CD-ROM model Internal 15mm, 5.
Table 1-3 System Specifications (continued) Item I/O ports (continued) Standard Optional One 3.5mm minijack mic-in port Microphone One 3.5mm minijack line-in port Audio CD player or other line-in devices One 3.5mm minijack line-out port Speakers or headphones Operating system Windows 95 Windows 3.1 Weight FDD model CD-ROM model (includes battery) 2.6 kg. (5.7 lbs.) 2.8 kg. (6.2 lbs.) Dimensions (main footprint) WxDxH 306mm x 228mm x 46mm (12.05” x 8.98” x 1.
1.2 System Board Layout 1.2.1 Main Board (PCB No: 96149-SC) Note: This switch setting is not for Extensa 610 use.
Figure 1-5 1-8 Main Board Layout (Bottom Side) Service Guide
1.2.2 Figure 1-6 1.2.
1.2.
1.2.
1.3 Jumpers and Connectors CN7 CN1 CN2 CN8 CN9 CN3 CN10 CN4 CN5 CN11 CN6 CN12 CN13 CN14 CN15 CN17 CN16 SW3 SW2 CN18 CN19 S1 Golden Finger for Debug Card NOTE: The shaded area (Black) indicates the position of the switch.
Table 1-4 CPU Voltage (S1) Settings CPU Voltage 2.35V 2.45V 2.9V 3.
1.4 Hardware Configuration and Specification 1.4.
1 2 3 4 5 6 7 1 1 1 2 2 2 2 1.4.
1.4.
Item Specification BIOS vendor Acer BIOS version v2.1 BIOS in flash EPROM (Y/N) Yes BIOS ROM size 256KB BIOS package type 32-pin TSOP Same BIOS for STN color/TFT color (Y/N) Yes The BIOS can be overwritten/upgradeable using the “AFLASH” utility (AFLASH.EXE). Please refer to software specification section for details. 1.4.8 System Memory Memory is upgradeable from 8 to 64 MB, employing 8-/16-/32-MB 64-bit soDIMMs (Small Outline Dual Inline Memory Modules).
The following table lists all possible memory configurations. Table 1-14 Memory Configurations 1.4.
1.4.10 Video Memory Table 1-15 Video RAM Configuration Item Specification DRAM or VRAM DRAM(EDO type) Fixed or upgradeable Fixed Memory size/configuration 1MB (256K x 16 x 2pcs) Memory speed 60ns Memory voltage 3.3V Memory package TSOP 1.4.11 Video Table 1-16 Video Hardware Specification Item Specification Video chip C&T65550B Working voltage C&T65550B: 3.3V C&T65550XX: 3.3V/5V (“XX” represents codes other than “A” (i.e.
1280x1024x16 86I 60 Y Y 1.4.11.
1.4.12 Parallel Port Table 1-19 Parallel Port Configurations Item Specification Number of parallel ports 1 ECP/EPP support Yes (set by BIOS setup) Connector type 25-pin D-type Location Rear side Selectable parallel port (by BIOS Setup) • • • • 1.4.
1.4.14 Audio Table 1-21 Audio Specifications Item Specification Chipset YMF715 Audio onboard or optional Built-in Mono or stereo Stereo Resolution 16-bit Compatibility SB-16 , Windows Sound System Mixed sound sources Voice, Synthesizer, Line-in, Microphone, CD Voice channel 8-/16-bit, mono/stereo Sampling rate 44.1 kHz Internal microphone No Internal speaker / quantity Yes / 2 pcs. Microphone jack Yes Headphone jack Yes 1.4.
1.4.16 Touchpad Table 1-23 Touchpad Specifications Item Specification Vendor & model name Synaptics TM1002MPU Power supply voltage (V) 5 ± 10% Location Palm-rest center Internal & external pointing device work simultaneously Yes Support external pointing device hot plug Yes X/Y position resolution (points/mm) 20 Interface PS/2 (compatible with Microsoft mouse driver) 1.4.
1.4.18 FDD Table 1-26 FDD Specifications Item Specification Vendor & model name Mitsumi D353F2 Floppy Disk Specifications Media recognition 2DD (720K) 2HD (1.2M, 3-mode) 2HD (1.44M) Sectors / track 9 15 18 Tracks 80 80 80 Data transfer rate (Kbits/s) 250 300 500 500 Rotational speed (RPM) 300 360 360 300 Read/write heads 2 Encoding method MFM Power Requirement Input Voltage (V) 1.4.
Item Specification Performance Specifications Data transfer rate (host-buffer, Mbytes/s) 16.6 (max., PIO mode 4) 16.6 (max., PIO mode 4) 16.6 (max., PIO mode 4) 16.6 (max., PIO mode 4) 5 ± 5% 5 + 5%, -10% 5 ± 5% 5 ± 5% DC Power Requirements Voltage tolerance (V) 1.4.20 CD-ROM Table 1-28 CD-ROM Specifications Item Vendor & Model Name Specification Panasonic UJDCD8730 Performance Specification Speed (KB/sec) 150 (normal speed) 1500 (10X speed) Access time (ms) 170 (Typ.
1.4.22 Charger To charge the battery, place the battery pack inside the battery compartment and plug the AC adapter into the notebook and an electrical outlet. The adapter has three charging modes: • Rapid mode The notebook uses rapid charging when power is turned off and a powered AC adapter is connected to it. In rapid mode, a fully depleted battery gets fully charged in approximately two hours.
Item Specification Vendor & model name Ambit T62.061.C.00 Input voltage (Vdc) 8~21 Output Rating Current (w/ load, A) 5V 3.3V 2.9V (2.35/2.45/2.9/3.1V) +12V +6V 5VSB 0~3.2 0~3.3 0~3.0 0~0.15 0~0.1 0.005 Voltage ripple (max., mV) 75 75 50 100 300 75 Voltage noise (max., mV) 100 100 100 200 500 100 6.5~8.2 4.5~6.2 3.3~5.0 for 2.9/3.1/2.35V/2.45V 14~20 7~9 - OVP (Over Voltage Protection, V) 1.4.
1.4.25 LCD Table 1-33 LCD Specifications Item Specification Vendor & model name HITACHI LMG9900ZWCC TORiSAN LM-FH53-22NAW IBM ITSV45E GOLDSTAR LP121S1-J LCD display area (diagonal, inch) 11.3 11.3 11.3 12.1 Display technology STN STN TFT TFT Resolution SVGA (800x600) VGA (800x600) SVGA (800x600) SVGA (800x600) Supported colors -- -- 262,144 colors 262,144 colors 30 (typ.) 30 (typ.) 100 (typ.) 100 (typ.) Brightness (cd/m ) 70 (typ.) 70 (typ.) 70 (typ.) 70 (typ.
1.4.26 AC Adapter Table 1-34 AC Adapter Specifications Item Vendor & model name Specification Delta ADP-45GB REV.E2 Input Requirements Nominal voltages (Vrms) 90 - 264 Frequency variation range (Hz) 47 - 63 Maximum input current (A, @90Vac, full load) 1.5 A Inrush current The maximum inrush current will be less than 50A and 100A when the adapter is connected to 115Vac(60Hz) and 230Vac(50Hz) respectively.
1.5 Software Configuration and Specification 1.5.1 BIOS The BIOS is compliant to PCI v2.1, APM v1.2, E-IDE and PnP specification. It also defines the hotkey functions and controls the system power-saving flow. 1.5.1.1 Keyboard Hotkey Definition The notebook supports the following hotkeys. Table 1-35 Hotkey Descriptions Hotkey Icon Fn-Esc Fn-F1 Fn-F2 ? Function Description Hotkey Escape Exits the hotkey control. Hotkey Help Displays the hotkey list and help. Press | to exit the screen.
1.5.1.
ON MODE Normal full-on operation STANDBY MODE The notebook consumes very low power in standby mode. Data remain intact in the system memory until battery is drained. The necessary condition for the notebook to enter standby mode is that the reserved disk space size for saving system and video memory is insufficient so the notebook is unable to enter hibernation mode.
A necessary condition for the notebook to enter hibernation mode is that the reserved space for saving system information on the hard disk must be larger than the combined system and video memory size. Under such conditions, the standby/hibernation hotkey acts as the hibernation hotkey. See the user’s manual for information on the Sleep Manager utility.
Table 1-37 Hibernation Mode Conditions and Descriptions Condition Description • “Hard Disk Drive” is not [Disabled] in System Security of BIOS SETUP. • “Hard Disk 0” is not [None] in Basic System Configuration of BIOS SETUP. • HDD has already located enough free contiguous disk space generated by the Sleep Manager and this free space is not corrupted. • Standby/Hibernation Timer times-out or Standby/Hibernation Hotkey pressed and there is no activity within 1/2 second.
Table 1-39 Hard Disk Standby Mode Conditions and Descriptions Condition Description The condition to enter HDD Standby Mode • Display Standby Timer times-out or LCD cover is closed. The condition of HDD Standby Mode • All the system components are on except HDD spindle motor The condition back to On Mode • Any access to HDD BATTERY LOW When the battery capacity is low and has no adapter plugged, the system will generate the following battery low warning: • Flash power LED with 4 Hz.
1.5.
1.
1.7 Environmental Requirements Table 1-42 Environmental Requirements Item Specification Temperature Operating (ºC) +5°C ~ +35°C Non-operating(ºC) -20°C ~ +60°C Humidity Operating (non-condensing) 20% ~ 80% Non-operating (non-condensing) 20% ~ 80% Operating Vibration (unpacked) Operating 5 - 25.6Hz, 0.38mm; 25.6 - 250Hz, 0.5G Sweep rate > 1 minute / octave Number of test cycles 2 / axis (X,Y,Z) Non-operating Vibration (unpacked) Non-operating 5 - 27.1Hz, 0.6G; 27.1 - 50Hz, 0.
1.8 Mechanical Specifications Table 1-43 Mechanical Specifications Item Specification Weight FDD model CD-ROM model (includes battery) 2.6 kg. (5.7 lb.) 2.8 kg. (6.2 lb.) Dimensions (main footprint) WxDxH 306mm x 228mm x 46mm (12.05” x 8.98” x 1.
C h a p t e r 2 Major Chips Description This chapter discusses the major chips used in the notebook. 2.1 Major Component List Table 2-1 Major Chips List Component Vendor Description M1521 Acer System data buffer M1523 Acer System controller chip M7101 Acer Power management unit 65550 C&T (Chips & Technology) Video controller TI PCI1131 Texas Instrument PCMCIA controller NS87336VJG NS (National Semiconductor) Super I/O controller YMF715 Yamaha Audio Chip T62.062.
2.2 ALI M1521 The ALADDIN-III consists of two chips, ALI M1521 and M1523 to give a 586 class system the complete solution with the most up-to-date feature and architecture for the new multimedia/multithreading operating system. It utilizes the BGA package to improve the AC characterization, resolves system bottleneck and make the system manufacturing easier.
• • UMA (unified memory architecture) • Dedicated UMA arbiter pins • Supports several protocols from major graphics vendors • SFB size : 512KB/1MB/2MB/3MB/4MB • CPU could access frame buffer memory through system memory controller • Alias address for frame buffer memory Fully synchronous 25/30/33 MHz 5V PCI interface • PCI bus arbiter: five PCI masters and M1523 supported • Dwords for CPU-to-PCI Memory write posted buffers • Convert back-to-back CPU to PCI memory write to PCI burst cycle •
2.2.
2.2.
2.2.
2.2.
2.2.6 Signal Descriptions Table 2-2 M1521 Signal Descriptions Signal Pin Type Description A[31:29] A[28:26] A[25:23] A[22:20] A[19:17] A[16:14] A[13:11] A[10:08] A[07:05] A[04:03] W8, W11, U11, Y10, Y9, V10, W9, W10, U9, U10, V9, U5, V5, W5, Y5, U6, W6, V6, Y6, U7, W7, Y7, V7, V8, Y8, Y12, U8, Y11, V11 I/O Host Address Bus Lines. A[31:3] have two functions.
Table 2-2 M1521 Signal Descriptions (continued) Signal Pin Type Description Host Interface M/IOJ H5 I Host Memory or I/O. This bus definition pin indicates the current bus cycle is either memory or input/ output. D/CJ T7 I Host Data or Code. This bus definition pin is used to distinguish data access cycles from code access cycles. W/RJ T9 I Host Write or Read. When WRJ is driven high, it indicates the current cycle is a write. Inversely, if WRJ is driven low, a read cycle is performed.
Table 2-2 M1521 Signal Descriptions (continued) Signal Pin Type Description DRAM Interface RASJ[6] / SCASJ[0] M16 O Row Address Strobe 6, or Synchronous DRAM CAS 0 (FPM/EDO/BEDO) of DRAM bank 6. SDRAM column address strobe (SDRAM) copy 0. RASJ[5:0] / SCSJ[5:0] N17, M17, E16, F16, F17, G17 I/O Row Address Strobes or synchronous DRAM chip select. These signals drives the corresponding RASJs of DRAMs or synchronous DRAM chip select[5:0].
Table 2-2 M1521 Signal Descriptions (continued) Signal Pin Type Description Secondary Cache Interface CCSJ/CB4 W16 O Synchronous SRAM chip select or Cache Address line 4 copy. This pin has two modes of operation depending on the type of SRAM selected via hardware strapping options or programming the CC register. GWEJ Y16 O Synchronous SRAM Global Write Asynchronous SRAM Write Enable. COEJ U15 O Synchronous/Asynchronous SRAM Output Enable.
Table 2-2 M1521 Signal Descriptions (continued) Signal Pin Type Description TRDYJ E8 I/O Target Ready. This indicates the target is ready to complete the current data phase of transaction. STOPJ E11 I/O Stop. This indicates the target is requesting the master to stop the current transaction. LOCKJ E5 I/O Lock Resource Signal. This indicates the PCI master or the bridge intends to do exclusive transfers. REQJ[3:0] D13, D11, D9, D7 I Bus request signals of PCI Masters.
Table 2-2 M1521 Signal Descriptions (continued) Signal Pin Type Description UMA Interface MGNTJ/ GNTJ[4] F7 O Memory Grant. This output connects to the MGNTJ of the GUI device. This pin can also be used as grant signal of the fifth PCI master. PRIO G15 I Priority. device. VCC F5, F6, G6, R6, R7, F14, F15, P15, R15, R16 P Vcc 3.3V VDD_5 E14 P Vcc 5.
2.3 ALI M1523 The M1523 is a bridge between PCI and ISA bus, providing full PCI and ISA compatible functions. The M1523 has Integrated System Peripherals (ISP) on-chip and provides advanced features in the DMA controller. This chip contains the keyboard controller, real-time clock and IDE master controller. This chip also supports the Advanced Programmable Interrupt controller (APIC) interface. One eight-byte bidirectional line buffer is provided for ISA/DMA master memory read/writes.
• • • 32-bit addressability • Provides compatible DMA transfers • Provides type F transfers Interrupt controller • Provides 14 interrupt channels • Independently programmable level/edge triggered channels Counter/Timers • • • • • • Provides 8254 compatible timers for system timer, refresh request, speaker output use Keyboard controller • Built-in PS2/AT keyboard controller • The specific I/O is used to save the external TTL buffer Real time clock • Built-in real-time clock • 128-by
2.3.
2.3.
2.3.4 Signal Descriptions Table 2-3 M1523 Signal Descriptions Signal Pin Type Description Clock and Reset PWG 17 I Power-Good Input. This signal comes from the power supply to indicate that power is available and stable. CPURST 49 O CPU Reset includes cold and warm reset 3.3V signal (connected to CPU INIT) RSTDRV 57 O CPU Cold Reset. 3.3V signal (connected to CPU RESET) OSC14M 43 I 14.318Mhz Clock Input. This is used for 8254 timer clock.
Table 2-3 M1523 Signal Descriptions (continued) Signal Pin Type Description PCI Interrupt Unit INTAJ_MI 67 I PCI Interrupt Input A or PCI interrupt polling input. INTBJ 68 I/O PCI Interrupt Input B or polling select_0 output. INTCJ 69 I/O PCI Interrupt Input C or polling select_1 output. INTDJ 70 I/O PCI Interrupt Input D or polling select_2 output. 66 O M1523 requests the ownership of the PCI bus.
Table 2-3 M1523 Signal Descriptions (continued) Signal Pin Type Description SA[16:0] 181, 185, 187, 188, 190, 192, 193, 195, 197, 199, 201, 203, 205, 207, 3, 4, 5 I/O ISA Slot Address Bus. connected to slot address. SBHEJ 6 I/O ISA Slot Byte-high Enable. In a CPU or PCI master cycle, this signal is generated by BE3J-BE0J and the chip’s internal control circuit. In a DMA cycle, it is generated by internal 8237. In a refresh cycle, it is generated by the internal refresh circuits.
Table 2-3 M1523 Signal Descriptions (continued) Signal Pin Type Description ISA Interface SMEMRJ / LMEGJ 176 O ISA System Memory Read. When the internal RTC is enabled, this signal indicates that the memory read cycle is for an address below 1-MB address. Otherwise, this pin only indicates an address below 1M byte. SMEMWJ / RTCAS 174 O ISA System Memory Write. When the internal RTC is enabled, this signal indicates that the memory write cycle is for an address below 1-MB address.
Table 2-3 M1523 Signal Descriptions (continued) Signal Pin Type Description Miscellaneous MSCLK 154 O Mouse Clock Output when the internal KBC is enabled. RTC32KI 16 I RTC 32.768K Osc1. This is crystal input and requires an external 32.768khz quartz crystal. RTC32KII 15 I RTC 32.768K Osc2. This is crystal input and requires an external 32.768khz quartz crystal. SIRQI 44 I Steerable IRQ Input 1 SIRQII/IRQ8J 45 I Steerable IRQ Input 2 when the internal RTC is enabled.
Table 2-3 M1523 Signal Descriptions (continued) Signal Pin Type 135, 132, 130, 128, 126, 124, 122, 119, 121, 123, 125, 127, 129, 131, 133, 136 I/O Description IDE Interface IDE_D[15:0] IDE ATA Data Bus Vcc and Vss VCC3 53 P Vcc 3.3V VCC5/VBAT 14 P RTC Battery Input VCC5 40, 72, 105, 120, 156, 208 P VCC 5.0V(VDD) Vss 1, 26, 52, 82, 104, 134, 157, 182 P Vss or Ground.
2.4 ALI M7101 (Power Management Unit) 2.4.
2.4.
2.4.3 Table 2-4 Pin Description M7101 Pin Descriptions Name No. Type Description PCI interface : (42) PCICLK 89 I PCI Clock. This is the PCI Bus interface CLK input signal. This clock frequency should not be more than 33 Mhz. It is used by internal PCI interface. AD[31:0] 91-98,29, 2025, 27, 28, 3037 I/O CBEJ[3:0] 99,10, 17,29 I PCI Bus Command and Byte enable. These are PCI bus commands at address phase and byte enable signals at data phase.
Table 2-4 M7101 Pin Descriptions (Continued) Name No. Type Description PMU Input event interface : (11) LBJ 47 I Low Battery. First stage battery low indication. If low is detected and Low Battery Timer is timeout, then battery low 1 SMIJ will be generated every programmed interval time until battery low 2 SMIJ is asserted or LB timer is reset. No debounce circuit is built in. Only low level is detected. LLBJ 48 I Low Low Battery. Second stage battery low indication.
Table 2-4 Name M7101 Pin Descriptions (Continued) No. Type Description PMU Input event interface : (11) PS2 50 I External PS2 MOUSE. This signal represents whether the PS2 MOUSE is plugged in or not. When a PS2 MOUSE is plugged in, a high to low transition will generate a SMIJ. When a PS2 MOUSE is pulled out, a low to high transition will generate a SMIJ as well. In addition, the signal status can be read from BEEPER offset 0CBh D1 register. Debounce circuit is built in.
Table 2-4 Name M7101 Pin Descriptions (Continued) No. Type Description PMU output interface (9) CCFT 57 O Backlight control. This signal is used to turn on/off LCD backlight. FPVEE will AND with offset 0D2h D0 to generate CCFT. That is, if both FPVEE and offset 0D2h D0 are high then CCFT will be high or 1Khz signal with programmed duty cycle by offset 0Fbh D[4:0]. Otherwise CCFT will be low. DISPLAY 58 O LCD Display On/Off control. This signal is used to control the LCD display ON/OFF.
Table 2-4 Name M7101 Pin Descriptions (Continued) No. Type Description General purpose I/O interface(24) General purpose I/O group A GPIOA6 (70) I Speak input. When offset 0F6h D6=‘1’, this pin will be speaker input. The input signal will xor with SPKCTL internally. (69) O External General Purpose I/O B write. When SQWO is pull low 4.7K, the GPIOA5 will become GPIOWA. External General purpose A R/W control pulse, When write index 0F0h with a byte or a word.
Table 2-4 Name M7101 Pin Descriptions (Continued) No. Type Description General purpose I/O interface(24) General purpose I/O group A GPIOA0 (64) O /GPIORAJ External General Purpose I/O A read. When SPKCTL is pull low 4.7K, the GPIOA0 will become GPIORAJ. External General purpose A Read control pulse, When Read index 0E1h with a byte or a word. A 74245 OEJ pulse will be generated at this pin. The 74245 output should be connected to PCI AD[23:16] if a byte command.
Table 2-4 Name M7101 Pin Descriptions (Continued) No. Type Description General purpose I/O interface(24) General purpose I/O group B GPIOB3 (84) I BRDYJ Input. When DISPLAY is pulled low, this pin will be BRDYJ input. It must be connected to CPU. (83) I INIT Input. When DISPLAY is pulled low, this pin will be INIT input. (82) I SMIJ Input. When DISPLAY is pulled low, this pin will be SMIJ input. (81) I SMIJ Input. When DISPLAY is pulled low, this pin will be INTR input.
Table 2-4 Name M7101 Pin Descriptions (Continued) No. Type Description General purpose I/O interface(24) General purpose I/O group C GPIOC5 (78) /EXTSW External suspend/resume switch. When offset 0F6h D10=0, this signal is GPIOC5. When D10=1, this signal will become EXTSW. External Suspend/Resume switch input. Pressing this switch will generate SMIJ to suspend or resume the system. When the system is at resume status(On, Doze), pressing this switch will enter Suspend status(Sleep).
Table 2-4 M7101 Pin Descriptions (Continued) Name No. Type Description Power Pins VDD5 x 3 11,59,76 P 5V VDD input VDD3 x 2 26,100 P 3.3V VDD input VDDS x 1 46 P 5V Suspend VDD input. This pin supplies to RI, RTC, HOTKEYJ, COVSW, SUSTATE, PWGD, SUSRSTJ pad. 1,19,38, 63,90 P VSS Ground. VSS x 5 2.4.4 • Different Pin definition setting SLED, CCFT, DISPLAY, SPKCTL, SQWO and GPIOC2 pins are all internal pull high 50K ohms.
When offset 0F6h, D5=1 and offset 0FBh, D7=1; GPIOB[7:0] and GPIOA[7:0] output some clocks for testing. The clocks are OTCOUNT, O16K, TCLK2, TCLK3, O128HZ, O16HZ, O8HZ, O4HZ, O2HZ, O1Hz, ELCOUNT, DZCOUNT, SLCOUNT, RICOUNT, LBCOUNT[1:0].
2.4.5 Table 2-7 Numerical Pin List M7101 Numerical Pin List No. Pin Name Type No.
2.4.6 Table 2-8 Alphabetical Pin List M7101 Alphabetical Pin List No. Pin Name Type No.
2.4.7 Function Description The function blocks of M7101 are as follows : 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. PCI Interface State Controller Timer Wake up event handler Activity monitor Battery monitor General Purpose Input/Output (GPIO) SMIJ Generator SUSPEND monitor APM monitor Rundown Emulation LCD control SLOWDOWN control PCI interface The PCI interface is running at PCICLK frequency. From the point of PCI bus, M7101 is a hidden component. There are no PCI configuration spaces built in.
Table 2-9 M7101 PCI Interface Lock Register Action I/O Port 0178h/0078h I/O Port 017Ah/007Ah Lock Read not available except offset 0D1h not available except offset 0D1h Lock Write not available except offset 0D1h not available except offset 0D1h Unlock Read available available Unlock Write available available State Machine for PCI Interface.
2.5 C&T 65550 High Performance Flat Panel/CRT VGA Controller The C&T65550 of high performance multimedia flat panel / CRT GUI accelerators extend CHIPS’ offering of high performance flat panel controllers for full-featured note books and sub-notebooks. The C&T65550 offers 64-bit high performance and new hardware multimedia support features. 2.5.
The C&T65550 offers a variety of programmable features to optimize display quality. Vertical centering and stretching are provided for handling modes with less than 480 lines on 480-line panels. Horizontal and vertical stretching capabilities are also available for both text and graphics modes for optimal display of VGA text and graphics modes on 800x600 and 1024x768 panels.
2.5.
2.5.4 Pin Descriptions Table 2-10 Pin# C&T 65550 Pin Descriptions Pin Name Type Description CPU Direct / VL-Bus Interface 207 RESET In Reset. For VL-Bus interfaces, connect to RESET#. For direct CPU local bus interfaces, connect to the system reset generated by the mother board system logic for all peripherals (not the RESET# pin of the processor).
Table 2-10 Pin# C&T 65550 Pin Descriptions (continued) Pin Name Type Description CPU Direct / VL-Bus Interface (continued) 43 BE0# (BLE#) In Byte Enable 0. Indicates data transfer on D7:D0 for the current cycle. 32 BE1# In Byte Enable 1. Indicates data transfer on D15:D8 for the current cycle. 21 BE2# In Byte Enable 2. Indicates data transfer on D23:D16 for the current cycle. 10 BE3# In Byte Enable 3.
Table 2-10 Pin# C&T 65550 Pin Descriptions (continued) Pin Name Type Description CPU Direct / VL-Bus Interface (continued) 51 50 49 48 47 46 45 44 41 40 38 37 36 35 34 33 20 19 18 17 16 15 14 13 8 7 6 5 4 3 2 1 D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O System Data Bus.
Table 2-10 Pin# C&T 65550 Pin Descriptions (continued) Pin Name Type Description PCI Bus Interface (continued) 31 PAR I/O Parity. This signal is used to maintain even parity across AD0-31 and C/BE0-3#. PAR is stable and valid one clock after the address phase. For data phases, PAR is stable and valid one clock after either IRDY# is asserted on a write transaction or TRDY# is asserted on a read transaction.
Table 2-10 Pin# C&T 65550 Pin Descriptions (continued) Pin Name Type Description PCI Bus Interface (continued) 30 SERR# (MCLKOUT) OD System Error. Used to report system errors where the result will be catastrophic (address parity error, data parity errors for Special Cycle commands, etc.). This output is actively driven for a single PCI clock cycle synchronous to CLK and meets the same setup and hold time requirements as all other bused signals.
Table 2-10 Pin# C&T 65550 Pin Descriptions (continued) Pin Name Type Description PCI Bus Interface (continued) 51 50 49 48 47 46 45 44 41 40 38 37 36 35 34 33 20 19 18 17 16 15 14 13 8 7 6 5 4 3 2 1 2-48 AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PCI Address
Table 2-10 Pin# C&T 65550 Pin Descriptions (continued) Pin Name Type Description PCI Bus Interface (continued) 43 32 21 10 C/BE0# C/BE1# C/BE2# C/BE3# In In In In Bus Command / Byte Enables. During the address phase.
Table 2-10 Pin# C&T 65550 Pin Descriptions (continued) Pin Name Type Description PCI Bus Interface (continued) 90 91 92 93 94 95 96 97 98 CA0 (P16) CA1 (P17) CA2 (P18) CA3 (P19) CA4 (P10) CA5 (P21) CA6 (P22) CA7 (P23) CA8 (BLANK) Out Out Out Out Out Out Out Out I/O Address bus for DRAM C. 99 HREF In Horizontal reference input for video capture.
Table 2-10 Pin# C&T 65550 Pin Descriptions (continued) Pin Name Type Description Display Memory Interface 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 MAD0 MAD1 MAD2 (CFG10) MAD3 (CFG11) MAD4 (CFG12) MAD5 (CFG13) MAD6 (CFG14) MAD7 (CFG15) MAD8 (PCI ROMD0) MAD9 (PCI ROMD1) MAD10 (PCI ROMD2) MAD11 (PCI ROMD3) MAD12 (PCI ROMD4) MAD13 (PCI ROMD5) MAD14 (PCI ROMD6) MAD15 (PCI ROMD7) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Memory data bus for DRAM A.
Table 2-10 Pin# C&T 65550 Pin Descriptions (continued) Pin Name Type Description Flat Panel Display Interface 71 72 73 74 75 76 78 79 81 82 83 84 85 86 87 88 P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out Out 8, 9, 12, or 16-bit flat panel data output. 18-bit and 24-bit panel interfaces may also be supported (see CA0-7 for P1623). 70 SHFCLK Out Shift Clock. Pixel clock for flat panel data. 67 FLM Out First Line Marker.
Table 2-10 Pin# C&T 65550 Pin Descriptions (continued) Pin Name Type Description Flat Panel Display Interface (continued) 55 RSET In Set point resistor for the internal color palette DAC. A 560 Ω 1% resistor is required between RSET and AGND. 59 56 AVCC AGND VCC GND Analog power and ground pins for noise isolation for the internal color palette DAC. AVCC should be isolated from digital VCC as described in the Functional Description of the internal color palette DAC.
Table 2-10 Pin# C&T 65550 Pin Descriptions (continued) Pin Name Type Description Power / Ground and Standby Control (continued) 66 63 89 DCC DGND DGND VCC GND GND 158 161 142 139 108 105 MVCCA MGNDA MVCCB MGNDB MVCCC MGNDC Power / Ground (Bus Interface) 5V±10% or 3.3V±0.3V. Power / Ground (Bus Interface) 5V±10% or 3.3V±0.3V.
BUS OUTPUT SIGNAL STATUS DURING STANDBY MODE Table 2-12 Bus Output Signal Status During Standby Mode 65550 Pin# Signal Name Signal Status 53 ACTI / A26 Driven Low 54 EBABKL / A27 Driven Low 24 LRDY# / RDY Tri-Stated 25 LDEV# Tri-Stated 51-44, 41-40, 38-33 D0-15 Tri-Stated 20-13, 8-1 D16-31 Tri-Stated S/TS stands for "Sustained Tri-state".
2.6 TI PCI1131 CardBus Controller 2.6.1 Overview The PCI1131 is a bridge between the PCI local bus and two PC Card sockets supporting both 16bit and 32-bit CardBus PC Cards, and is compliant with the PCI Local Bus Specification Revision 2.1 and PCMCIA's 1995 PCI Card Standard. The PCI 1131 PC Card interface recognizes and identifies PC Cards installed at power-up, run-time, and switches protocols automatically to accommodate 16-bit and 32-bit cards.
2.6.2 Architecture The Texas Instruments PCI1131 is a high-performance PCI-to-PC Card controller that supports two independent PC Card sockets compliant with the1995 PC Card Standard. The PCI1131 provides a rich set of features which make it the best choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1995 PC Card Standard retains the 16-bit PC Card specification defined in PCMCIA Release 2.
• Packaged in a 208-pin TQFP • Multi-function PCI Device with Separate Configuration Spaces for each Socket • Five PCI Memory Windows and Two l/O Windows Available to each PC Card16 Socket • Two l/O Windows and Two Memory Windows Available to each CardBus socket • CardBus Memory Windows can be Individually selected prefetchable or non-prefetchable • ExCA™-Compatible Registers Are Mapped in Memory andfilO Space • Texas Instruments (TI™) Extension Registers Mapped in the PCI Configuration Space
2.6.
Figure 2-12 2-60 Functional block diagram - CardBus Card Interface Service Guide
2.6.
Figure 2-14 2-62 PCI-to-CardBus terminal assignments Service Guide
2.6.6 Terminal Functions Table 2-13 PCI1131 Pin Descriptions TERMINAL NAME NO. I/O FUNCTION TYPE PCI System Terminals PCLK 165 I PCI Bus clock. The PCI bus clock provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK. RSTIN 166 I PCI Reset. When the RSTIN signal is asserted low it causes the PCI1131 to tri-state all output buffers and reset all internal registers. When asserted, the 1131 device is completely nonfunctional.
Table 2-13 PCI1131 Pin Descriptions (Continued) TERMINAL NAME NO. I/O FUNCTION TYPE PCI Address and Data Terminals C/BE3 180 I/O 8us commands and byte enables. These are muitiplexed on the same PCI terminals. During the address phase, C/BE-0 define the bus command. During the data phase, C /ENEW-O are used as byte enables. The byte enables determine which byte lanes carry meaningful data.
Table 2-13 PCI1131 Pin Descriptions (Continued) TERMINAL NAME NO. I/O FUNCTION TYPE PCI Interface Control Terminals TRDY 196 I/O Target ready. Indicates the PCI 1131 ability to complete the current data phase of the transaction. TRDY is used in conjunction with IRDY. A data phase is completed on any clock where both TRDY I/O are sampled asserted. During a read, TRDY indicates that valid data is present on AD31-0. During a write, TRDY indicates the PCI1131 is prepared to accept data.
Table 2-13 PCI1131 Pin Descriptions (Continued) TERMINAL Name Slot Slot A+ B≠ ≠ I/O FUNCTION TYPE 1 6-bit PC Card Address and Data (Slots A and B) D15 93 27 D14 91 25 D13 89 23 D12 87 20 D11 84 18 D10 147 81 D9 145 79 D8 142 77 D6 90 24 D5 88 21 D4 85 19 D3 83 17 D2 146 80 D1 144 78 D0 141 76 I/O PC Card Data. 16-bit PC Card data lines. D15 is the most significant bit.
Table 2-13 PCI1131 Pin Descriptions (Continued) TERMINAL Name Slot Slot A+ B≠ ≠ I/O FUNCTION TYPE 1 6-bit PC Card Interface Control Signals (Slots A and B) BVD2 71 137 I (SPKR) Battery Voltage Detect 2. Generated by 16-bit memory PC Cards that include batteries. BVD2 is used with BVD 1 as an indication of the condition of the batteries on a memory PC Card. Both BVD 1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and needs to be replaced.
Table 2-13 PCI1131 Pin Descriptions (Continued) TERMINAL Name Slot Slot A+ B≠ ≠ I/O FUNCTION TYPE 1 6-bit PC Card Address and Data (Slots A and B) IORD 99 33 O I/O Read. LORD is asserted by the PCI1131 to enable 16-bit l/O PC Card data output during host I/O read cycles. (DMA Write) This pin is used as the DMA write strobe during DMA operations from a 16-bit PC Card which supports DMA. The PCI 1131 asserts this signal during DMA transfers from the PC Card to host memory.
Table 2-13 PCI1131 Pin Descriptions (Continued) TERMINAL Name Slot Slot A+ B≠ ≠ I/O FUNCTION TYPE 1 6-bit PC Card Interface Control Signals (Slots A and B) WP 139 73 I (IOIS16) Write Protect. This signal applies to 16-bit Memory PC Cards. WP reflects the status of the write-protect switch on 16-bitmemory PC Cards. For 16-bit l/O cards, WP is used for the 16-bit port ( IOIS16) function. The status of the signal can be read from the interface status register. (I/O is 16 bits).
Table 2-13 PCI1131 Pin Descriptions (Continued) TERMINAL Name Slot Slot A+ B≠ ≠ I/O FUNCTION TYPE CardBus PC Card Address and Data Signals (Slots A and B) CC/BE0 94 28 CC/BE1 104 39 CC/BE2 117 52 CC/BE3 130 63 CPAR 41 106 I/O CardBus PC Card Command and Byte Enables. These signals are multiplexed on the same pin. During the address phase of the transaction, CC/BE3 0 define the bus command. During the data I/O phase transaction, CC/BE3-0 are used as Byte Enables.
Table 2-13 PCI1131 Pin Descriptions (Continued) TERMINAL Name Slot Slot A+ B≠ ≠ I/O FUNCTION TYPE CardBus PC Card Interface Control Signals (Slots A and B) CBLOCK 107 42 I/O CardBus Lock. This is an optional signal used to lock a particular address, ensuring a bus initiator exclusive access. NOTE: This signal is not supported on the PCI 1131. CDEVSEL 111 47 I/O CardBus Device Select.
Table 2-13 PCI1131 Pin Descriptions (Continued) TERMINAL Name Slot Slot A+ B≠ ≠ I/O FUNCTION TYPE CardBus PC Card Interface Control Signals (Slots A and B) CREQ 127 61 I CardBus Request. This signal ir1dicates to the arbiter that the CardBus PC Card desires use the CardBus bus. CGNT 110 46 O CardBus Grant. This signal is driven by the PCI 1131 to grant a CardBus PC Card access to the CardBus bus after the current data transaction has completed CPERR 108 43 I/O CardBus Parity Error.
Table 2-13 PCI1131 Pin Descriptions (Continued) TERMINAL NAME NO I /O TYPE FUNCTION O Interrupt Request 3 and Interrupt Request 4. These terminals may be connected to either PCI or ISA interrupts. These terminals are software configurable as IRQ3 or T1VTA, and as IRQ4 or T1~. When configured for IRQ3 and IRQ4, these terminals should be connected to the ISA IRQ programmable interrupt controller.
Table 2-13 PCI1131 Pin Descriptions (Continued) TERMINAL NAME NO I /O TYPE FUNCTION I/O Interrupt Request 15. This terminal indicates an interrupt request from one of the PC Cards. RI_OUT allows the RI input from the 1 6bit PC Card, CSTSCHG from CardBus Cards or PC Card removal events to be output to the system. This signal is configured in the Card Control Register of the TI Extension Registers.
2.7 NS87336VJG Super I/O Controller The PC87336VJG is a single chip solution for most commonly used I/O peripherals in ISA, and EISA based computers. It incorporates a Floppy Disk Controller(FDC), two full featured UARTs, and an IEEE 1284 compatible parallel port Standard PC-AT address decoding for all the peripherals and a set of configuration registers are also implemented in this highly integrated member of the Super l/O family.
• • • • • • The Bidirectional Parallel Port: • Enhanced Parallel Port(EPP) compatible • Extended Capabilities Port(ECP) compatible, including level 2 support • Bidirectional under either software or hardware control • Compatible with ISA, and EISA, architectures • Ability to multiplex FDC signals on parallel port pins allows use of an external Floppy Disk Drive(FDD) • Includes protection circuit to prevent damage to the parallel port when a connected printer is powered up or is operated at
• • Plug and Play Compatible: • 16 bit addressing(full programmable) • 10 selectable IRQs • 3 selectable DMA Channels • 3 SIRQ Inputs allows external devices to mapping IRQs 100-Pin TQFP package - PC87336VJG 2.7.2 Block Diagram Config.
2.7.
2.7.4 Pin Description Table 2-14 Pin NS87336VJG Pin Descriptions No. I/O Description A15-A0 67, 64, 62-60, 29, 1928 I Address. These address lines from the microprocessor determine which internal register is accessed. A0-A15 are don't cares during DMA transfer. /ACK 83 I Parallel Port Acknowledge. This input is pulsed low by the printer to indicate that it has received the data from the parallel port. This pin has a nominal 25 KΩ pull-up resistor attached to it.
Table 2-14 Pin NS87336VJG Pin Descriptions (continued) No. I/O Description /CS0, /CS1 51, 3 O Programmable Chip Select. /CS0, 1 are programmable chip select and/or latch enable and/or output enable signals that can be used as game port, I/O expand, etc. The decoded address and the assertion conditions are configured via the 87336VJG’s configuration registers. /CTS1, /CTS2 72, 64 I UARTs Clear to Send. When low, this indicates that the modem or data set is ready to exchange data.
Table 2-14 Pin NS87336VJG Pin Descriptions (continued) No. I/O Description DENSEL (Normal Mode) 46 O FDC Density Select. DENSEL indicates that a high FDC density data rate (500 Kbs, 1 Mbs or 2 Mbs) or a low density data rate (250 or 300 Kbs) is selected. DENSEL is active high for high density (5.25-inch drives) when IDENT is high, and active low for high density (3.5-inch drives) when IDENT is low. DENSEL is also programmable via the Mode command. DENSEL (PPM Mode) 76 O FDC Density Select.
Table 2-14 Pin NS87336VJG Pin Descriptions (continued) No. I/O Description /DRV2 47 I FDD Drive2. This input indicates whether a second disk drive has been installed. The state of this pin is available from Status Register A in PS/2 mode. (See PNF for further information). /DSKCHG (Normal Mode) 30 I Disk Change. The input indicates if the drive door has been opened. The state of this pin is available from the Digital Input Register.
Table 2-14 Pin NS87336VJG Pin Descriptions (continued) No. I/O Description IORCHDY 51 O I/O Channel Ready. When IORCHDY is driven low, the EPP extends the host cycle. IRQ3, 4 IRQ5-7 IRQ9-11 IRQ12, 15 (PnP Mode) 99, 98 96-94, 55-57, 66, 58 I/O Interrupt 3, 4, 5, 6, 7, 9, 10, 11, 12, and 15. This pin can be a totempole output or an open-drain output. The interrupt can be sourced by one of the following: UART1 and/or UART2, parallel port, FDC, SIRQI1 pin, SIRQI2 pin or SIRQI3 pin.
Table 2-14 NS87336VJG Pin Descriptions (continued) Pin No. /MSEN0 /MSEN1 (Normal Mode) 50, 49 I Media Sense. These pins are Media Sense input pins when bit 0 of FCR is 0. Each pin has a 10 KΩ internal pull-up resistor. When bit 0 of FCR is 1, these pins are Data Rate output pins and the pull-up resistors are disabled. /MSEN0 /MSEN1 (PPM Mode) 86, 84 I Media Sense. These pins gives additional Media Sense signals for PPM Mode and PNF = 0.
Table 2-14 Pin /RI1 /RI2 NS87336VJG Pin Descriptions (continued) No. 68, 60 I/O I Description UARTs Ring Indicator. When low, this indicates that a telephone ring signal has been received by the modem. The /RI signal is a modem status input whose condition is tested by the CPU by reading bit 6 (RI) of the Modem Status Register (MSR) for the appropriate serial channel. Bit 6 is the complement of the RI signal.
Table 2-14 NS87336VJG Pin Descriptions (continued) Pin No. I/O Description TC 4 I Terminal Count. Control signal from the DMA controller to indicate the termination of a DMA transfer. TC is accepted only when FDACK is active. TC is active high in PC-AT and Model 30 modes, and active low in PS/2 mode. /TRK0 (Normal Mode) 35 I FDC Track 0. This input indicates the controller that the head of the selected floppy disk drive is at track zero. /TRK0 (PPM Mode) 91 I FDC Track 0.
2.8 Yamaha YMF715 Audio Chip YMF715-S (OPL3-SA3) is a single audio chip that integrates OPL3 and its DAC, 16 bit Sigmadelta CODEC, MPU401 MIDI interface, joystick with timer, and a 3D enhanced controller including all the analog components which is suitable for multi-media application. This LSI is fully compliant with Plug and Play ISA 1.0a, and supports all the necessary features, i.e. 16 bit address decode, more IRQs and DMAs in compliance with PC'96. This LSI also supports the expandability, i.e.
2.8.
2.8.
Table 2-15 YMF715 Descriptions (Continued) Pin name Pins I/O Type Size Function CMOS 2mA Refer to “Multi-purpose pins” section TTL 4mA Refer to “multi-purpose pins” section Multi-purpose Dins: 13 pins SEL2-0 3 MP9-0 I+ l0 I+/O Others: 27 pins GPO - GP3 4 IA - - Game Port GP4- GP7 4 I+ Schmitt 2mA Game Port RXD 1 I+ Schmitt 2rnA MIDI Data Receive TXD 1 O TTL 4mA MIDI Data Transfer /VOLUP 1 I+ Schmitt 2mA Hardware Volume (Up) /VOLDW l I+ Schmitt 2mA Hardwa
2.9 T62.062.C Battery Charger 2.9.1 Overview Ambit T62.062.C.00 charger is designed exclusively for TI Extensa 610 notebook computer as a power management and battery charger module which can charge a 9 cells Nickel-Metal Hydride (NiMH) or 9 cells with 3’s parallel and 3’s serial Lithium Ion(LIB) Battery pack.
• • Max. T • Safety charging timer • Battery temperature constantly monitoring • Over voltage protect 13V Providing low battery warning signals when the system using battery as the main power source 2.9.3 Absolute Maximum Ratings Table 2-16 T62.062.C Absolute Maximum Ratings Table Parameter Maximum Ratings Supply voltage ( Adapter) 0V to +24V Output current 3A Total sink current of all O/P pin (output pin to DC/DC not included) 15mA Charge current 1.
Table 2-17 T62.062.C Electrical Characteristics Table (Continued) Parameter Symbol Condition MIN TYP MAX UNITS AC source voltage > 8V 4.5 5 5.25 V 10 mA 5.25 V (Low) 0.7 V (Supply current) 100 uA OUTPUT AC Source input Signal AD5V (Voltage) (Supply current) Battery in use (High) BAT-IN-USE# Power Output DCBAT OUT Charge Indicator BT-QCHG @I load=100uA 2.7 5 - - 3 A (High) 3.5 5 5.25 V (Low) - - 0.8 V (Supply current) - - 100 uA (High) 2.7 5 5.
Table 2-17 T62.062.C Electrical Characteristics Table (Continued) Parameter Symbol Condition MIN TYP MAX UNITS SAFETY OPERATION Over voltage protect by Software NiMH 16.2 V 13 V LiB_lon Note 1: External Adapter: Voltage limit 20V1V with maximum 24V over voltage as well as over current protection. 2.9.
2.9.6 Pin Description Table 2-18 T62.062.C Pin Description table Item Pin Name I/O Description SAFETY OPERATION 1 DC_BAT_OUT O/P .adapter power input and battery power output terminal( with 5 A short circuit protection) 2 DC_BAT_OUT O/P same as pin 1 3 DC_BAT_OUT O/P same as pin 1 4 DC_BAT_OUT O/P same as pin 1 5 GND ground 6 GND ground 7 PERIPHERAL I/P system power on ,input a high pulse. user have different way to turn on sysem by peripheral device.
2.9.7 Functions Description 2.9.7.1 Charge Function A. FOR NIMH BATTERY When the charger module charges a 9 cells NiMH battery, 0V and T/ t, max T and - v detentions will be used as the main methods to determine the full charged battery. To ensure safety for the battery and system, fast charging NiMH battery after long period of storage time, the module will disable 0V detection during a short “ hold-off” period at the start of fast charging.
When system on if Adapter not inserted and battery voltage lower than BL3 voltage , then system will be turned off by the charger module. In addition, when system sends a ‘disable’ signal to charger module, system will be turned off by the charger module immedietly. 2.9.7.3 Safety Concerns For safety, the charger module inhibits charging until the battery voltage and temperature are within the configured ranges.
2.10 T62.061.C DC-DC Converter This compact, high efficiency DC/DC Converter features +5V, +3.3V, 2.35V/2.45V/2.9V/3.1V, +12V and +6V five outputs up to 22 watts. And it accepts input from 7V to 21V, suitable for 3 cells Lithium Ion or 10 cells NiMH battery input Pentium based Notebook PC. The converter also supplies P.G. signal, 2.35V/2.45V/2.9V/3.1V switch for CPU and ON/OFF control. 2.10.1 Pin Diagram Figure 2-19 2.10.2 T62.061.C Pin Diagram Pin Assignment Table 2-19 T62.061.
2.10.3 Specifications Input: • DC BATT_IN:7V-8V DC Output: • +5V :Load :0~2A • +12V :Load :0~0.12A • The other conditions same as 2.2.1 Input: • DCBATT_IN :8V-21V DC Output: • • • +5V: Load : 0A-3.2A Regulation: +5%, -5% • Ripple: 50mV (max) • Noise: 100mV (max) • OVP: 6.5-8.2V • Short-circuit protection • Fuse protection • *Ripple(max)=75mV when regulate in IDLE mode +3.3V: Load : 0A-3.
• • • • +2.35V:(2.45V) Load • Regulation: +5%, -4% • Ripple: 50mA (max) • Noise: 100mV (max) • OVP: 3.3-5.0V • Short-circuit protection • Fuse protection • *Ripple(max)=75mV when regulate in IDLE mode +12V : Load : 0A-0.15A Regulation: +/-5% • Ripple: 100mV (max) • Noise: 200mV (max) • OVP: 14-20V • *The +12V max load condition is available only when the +5V output load is greater than 0.5A. +6V : Load : 0A~0.1A Regulation: 5.5V~7.
Output filter capacitor The recommended value is 30uF/Amps TAN or OS-CON CAP. Efficiency: 90%(MIN) at 12V input and 5V/1.5A , 3.3V/0.8A , 2.9V/0.6A load.
2.11 T62.064.C DC-AC Inverter (11.3") THIS IS A DC-AC INVERTER UNIT TO DRIVE BACKLIGHT CCFT FOR NOTEBOOK COMPUTERS Table 2-20 MAXIMUM RATINGS ITEM SYMBOL MIN MAX UNIT INPUT VOLTAGE Vin 7 22 V INPUT CURRENT Iin -- 0.6 A 2.11.1 REMARK Electrical Specifications Electrical Characteristics Table 2-21 Electrical Characteristics ITEM SYMBOL MIN TYP MAX UNIT REMARK INPUT VOLTAGE Vin 7.0 -- 22.
Operation Conditions • OPERATING TEMPERATURE 0 TO +50 • OPERATING HUMIDITY 90% MAX. R.H • STORAGE TEMPERATURE 10 TO +85 • STORAGE HUMIDITY 90% MAX. R.H • MTBF 50000 HRS 2.11.2 Pin & Connector Assignment J1: 52103-1217 (MOLEX) Table 2-22 Pin Description PIN NO. SYMBOL DESCRIPRION 1 DCBATTIN DC (7.0V ~ 21.0V) 2 GND POWER GND 3 CCFTON PWM SIGNAL FOR ON/OFF AND BRIGHTNESS CONTROL 4 DATA ID X24C02 DATA 5 +5.0V +5.0V ± 10% 6 SGND LOGIC GND FOR X24C02 7 N.C. 8 CK 9 N.
2.11.3 Top Overlay Figure 2-20 2.11.4 Bottom Overlay Figure 2-21 2-104 T62.064.C DC-AC Inverter Top Overlay diagram T62.064.
2.12 T62.066.C DC-AC Inverter (12.1") This is a DC-AC inverter unit to drive Backlight CCFT for notebook computers Table 2-23 MAXIMUM RATINGS ITEM SYMBOL MIN MAX UNIT INPUT VOLTAGE Vin 7 21 V INPUT CURRENT Iin -- 0.65 A 2.12.1 REMARK Electrical Specifications Electrical Characteristics Table 2-24 Electrical Characteristics ITEM SYMBOL MIN TYP MAX UNIT REMARK INPUT VOLTAGE Vin 7.0 -- 21.
2.12.2 Pin & Connector Assignment J1: 52103-1217 (MOLEX) Table 2-25 J1: 52103-1217 (MOLEX) Pin Description PIN NO. SYMBOL DESCRIPRION 1 DCBATTIN DC (7.0V ~ 21.0V) 2 GND POWER GND 3 CCFTON PWM SIGNAL FOR ON/OFF AND BRIGHTNESS CONTROL 4 DATA ID X24C02 DATA 5 +5.0V +5.0V ± 10% 6 SGND LOGIC GND FOR X24C02 7 N.C. 8 CK 9 N.C. 10 VEE VEE OUTPUT 11 CTEN CONTRAST ON/OFF TTL LEVEL ″H″ ON 12 CTVREN PWM SIGNAL FOR CONTRAST VOLTAGE CLOCK FOR X24C02 J2:SM02(8.
2.12.3 Top Overlay Figure 2-22 2.12.4 T62.066.C DC-AC Inverter Top Overlay diagram Bottom Overlay Figure 2-23 T62.066.
C h a p t e r 3 BIOS Setup Information The notebook has a BIOS setup utility that allows you to configure the notebook and its hardware settings. This chapter tells how to use the Setup utility and describes each parameter item in the setup screens. The notebook is also bundled with Windows 95-based notebook management utility similar in function with the BIOS Setup utility called the Notebook manager. See section 5.3 for details. 3.
3.2 Entering Setup Press F2 during POST to enter Setup. The BIOS Utility main screen displays. Setup Utility Basic System Settings System Security Power Management Settings Load Setup Default Settings ↑↓=Move Highlight Bar, ↵=Select, Esc=Exit There are four main menu items: • Basic System Settings • System Security • Power Management Settings • Load Setup Default Settings Read through the Setup Screen Notes before navigating the Setup screens.
• When you press Esc to exit the Setup utility, the following prompt appears: Do you want to save CMOS data? [Yes] • [No] Select [Yes] to save the changes you made to the configuration values or [No] to abandon the changes and retain the current values.
3.3 Basic System Configuration Basic System Configuration has a one-page screen display illustrated below. Basic System Settings Date ----------------------Time ----------------------Floppy Disk A -------------Floppy Disk B -------------Hard Disk (1160 MB) -------Large Hard Disk Capacity --Memory Test ---------------Boot Display --------------Quiet Boot ----------------- [Dec 06,1996] [10:00:00] [1.44 MB 3.
3.3.5 Memory Test The notebook can test main memory for errors when you turn it on. The default setting, [Disabled], allows the notebook to bypass the memory test and speed up the self-test procedure. 3.3.6 Boot Display If you connect an external monitor, you can switch display between the LCD and the external display. This parameter determines which display device the notebook uses on boot-up. Table 31 describes the different settings.
3.
3.4.3 System Boot Drive Control This parameter determines which drive the notebook boots from when you turn it on. following table lists the three possible settings. Table 3-4 The System Boot Drive Control Settings Setting Description Drive A Then C (default) Notebook boots from floppy drive A. If there is no system disk in drive A, the notebook boots from hard disk C. If the hard disk is a non-system disk, an error message appears. Drive C Then A Notebook boots from hard disk C.
3.4.5 Serial Port 1 Base Address The serial port can accommodate a modem, serial mouse, serial printer, or other serial devices. The default setting for the serial port base address is 3F8h(IRQ 4)1. Other options include: • 2F8h(IRQ 3) • 3E8h(IRQ 4) • 2E8h(IRQ 3) • Disabled Make sure the serial port base address does not conflict with the address used by a PCMCIA card, if one is installed. 3.4.
The default setting is [Standard and Bidirectional]. If you set EPP as the parallel port operation mode, do not use 3BCh as the parallel port base address; otherwise, I/O conflicts may occur. ECP DMA Channel Set the ECP DMA Channel parameter if you set the Parallel Port Operation Mode to [Enhanced Capabilities Port(ECP)]. The default value, with ECP selected, is [0]. 3.4.8 Passwords Two passwords are implemented in this notebook.
3.4.9 CardBus Support The notebook comes pre-installed with a Windows 95 version which has built-in support for CardBus. In this case, CardBus Support is not needed and set to [Disabled]. If in case you install an older version of Windows 95 which does not have built-in Cardbus driver support, you need to enable this parameter. The default setting is [Disabled]. To verify your Windows 95 version, access the System icon in the Control Panel.
3.5 Power Management Settings Besides accessing this screen from POST (F2), you can also press Fn-F6 during runtime to access this section of Setup.
The valid values for this timer range from 1 to 15 minutes with default set at [1]. Select [Off] to disable the timer. 3.5.4 System Sleep Timer This parameter enables you to set a timeout period for the notebook to enter either standby or hibernation mode. The System Sleep Mode parameter determines which sleep mode the notebook will enter into. The valid values for this timer range from 1 to 15 minutes with default set at [3]. Select [Off] to disable the timer. 3.5.
3.5.9 Battery-low Warning Beep This parameter allows you to enable or disable the warning beep generated by the notebook when a battery-low condition occurs. The default setting is [Enabled]. 3.5.10 Sleep Upon Battery-low This parameter enables the notebook to enter standby or hibernation mode when a battery-low condition takes place. The default setting is [Enabled].
3.6 System Information Reference If you access Setup during runtime (Fn-F6), pressing PgDn after the Power Management Settings screen displays a summary of your notebook’s components and settings. System Information Reference CPU ID : Pentium Internal Cache : 16KB, Enabled CPU Clock : 133 MHz External Cache : 256KB, Enabled System DRAM : 16 MB Pointing Device : Detected Video DRAM : 1 MB Internal KB : 85 key Floppy Disk A : 1.
Table 3-6 System Status Descriptions Item Description CPU ID Shows the processor type CPU Clock Shows the processor speed System memory Shows the total system memory Video memory Shows the total video memory Floppy Disk A Shows the floppy drive A type Security Floppy Disk B Security Hard Disk Security Shows floppy drive A security setting Shows the floppy drive B type Shows floppy drive B security setting Shows the IDE drive type and size and its security setting Shows hard disk drive security
3.7 Load Setup Default Settings Selecting this option allows you to load all the default settings. The default settings are the values initially stored in CMOS RAM intended to provide high performance. If in the future, you change these settings, you can load the default settings again by selecting this option. When you select this option, the following prompt appears: Load Setup Default Settings Are you sure? [Yes] [No] Select [Yes] to load the default settings or [No] to abort the operation.
C h a p t e r 4 Disassembly and Unit Replacement This chapter contains step-by-step procedures on how to disassemble the notebook computer for maintenance and troubleshooting. To disassemble the computer, you need the following tools: • Wrist grounding strap and conductive mat for preventing electrostatic discharge • Flat-bladed screwdriver • Phillips screwdriver • Hexagonal screwdriver • Tweezers • Plastic stick The screws for the different components vary in size.
4.1 General Information 4.1.1 Before You Begin Before proceeding with the disassembly procedure, make sure that you do the following: 1. Turn off the power to the system and all peripherals. 2. Unplug the AC adapter and all power and signal cables from the system. 3. Remove the battery pack from the notebook by (1) pressing the battery compartment cover release button, and sliding out the cover. Then (2) pull out the battery pack.
4.1.2 Connector Types There are two kinds of connectors on the main board: • Connectors with no locks Unplug the cable by simply pulling out the cable from the connector. • Connectors with locks You can use a plastic stick to lock and unlock connectors with locks. The cables used here are special FPC (flexible printed-circuit) cables, which are more delicate than normal plastic-enclosed cables. Therefore, to prevent damage, make sure that you unlock the connectors before pulling out the cables.
4.1.3 Disassembly Sequence The disassembly procedure described in this manual is divided into four major sections: • Section 4.2: Replacing Memory • Section 4.3: Removing the hard disk drive • Section 4.4: Removing the keyboard • Section 4.5: Disassembling the inside frame assembly • Section 4.6: Disassembling the display The following table lists the components that need to be removed during servicing.
Figure 4-3 Disassembly Sequence Flowchart Disassembly and Unit Replacement 4-5
4.2 Replacing Memory Follow these steps to insert memory modules: 1. Turn the computer over to access the base. 2. Remove the screw from the memory expansion door and remove the door. The memory door screw is part of the memory door and does not separate from the memory door. Figure 4-4 Removing the Memory Door 3. Remove the memory modules from its shipping container. 4. Align the connector edge of the memory module with the key in the connector.
5. Replace the memory expansion door and screw in place. Sleep Manager must be run after installing additional memory for the computer to hibernate properly. If Sleep Manager is active, it will automatically adjust the hibernation file on your notebook. If you are using an operating system other than Windows 95 or DOS, you may need to re-partition your hard disk drive to allow for the additional memory. Check with your system administrator. 4.
3. You will see a tape handle attached to the hard disk drive. Pull out the hard disk drive using the tape handle. Be careful pulling the hard disk drive out. Make sure the connector of the hard disk drive transfer board doesn’t loosen while removing the hard disk drive. Figure 4-7 4. Removing the Hard Disk Drive Store the hard disk drive in an antistatic bag. If you want to install a new hard disk drive, reverse the steps described above.
4.4 Removing the Keyboard Follow these steps to remove the keyboard: 1. Slide out (1) and pull up (2) the two display hinge covers on both sides of the notebook. Figure 4-8 2. Removing the Display Hinge Covers Unplug the keyboard connectors (CN1 and CN2) from the keyboard connection board. Set aside the keyboard.
4.5 Disassembling the Inside Frame Assembly This section discusses how to disassemble the housing, and during its course, includes removing and replacing of certain major components like the internal drive (CD-ROM or floppy), CPU and the main board. Follow these steps: 4.5.1 Removing the Heat Sink Assembly Remove the four screws that secure the heat sink to the housing.
4.5.2 Removing the Internal Drive 1. Pull up and remove the FDD/CD module latches. 2. Unplug the internal drive cable (CN14/CN17 for CD-ROM or CN14 for FDD). 3. Pull out the internal drive and set it aside. Ensure the drive cables do not become hooked on the inside frame assembly when removing and reinstalling the drive.
4.5.3 Replacing the CPU The unique ZIF (zero insertion force) socket allows you to easily remove the CPU. Follow these steps to remove the CPU and install a replacement CPU. See figure below. 1. Insert a flat-blade screwdriver into the opening at the left end of the socket (labeled OPEN) and push towards the other end of the socket. 2. Pull out the CPU. Then insert the replacement CPU. Insure the CPU is properly keyed before pressing it into the socket. 3.
4.5.4 1. Removing the Display Remove the two screws that secure the display cable to the motherboard. Then unplug the display cable. Figure 4-13 2. Unplugging the Display Cable Remove the four display hinge screws. Then detach the display from the main unit and set aside.
4.5.5 1. Detaching the Top Cover Screws found on the lower case secure the top cover with the lower. However, you may not need to remove all six screws. Follow the discussion below for details. • If you only want to remove the top cover from the lower case, remove all screws except for the encircled ones in this figure below. • If you intend to remove the motherboard with the chasis from the lower case, remove all screws.
2. Remove three screws near the display hinge screw holes and one screw near the PC card slots. Before you detached the top cover make sure that you unplug the cable for the CN19 (touch pad). Unsnap the top cover from the base assembly and set aside.
4.5.6 Removing the Base Assembly Remove four screws that secure the inside frame assembly to the base assembly. Then detach the inside frame assembly from the base assembly.
4.5.7 1. Removing the Motherboard Remove the fan by (3) removing the sticker and (4) unplugging the fan cable (CN9). Figure 4-18 Removing the Fan When installing the fan, the fan hole should face the rear of the unit to draw thermal air out of the system. 2. Remove the audio board by (1) unplugging the audio board connector (CN5), and then (2) pulling up the audio board.
3. Unplug the battery connector board cable (CN18). Figure 4-20 4. Removing the Battery Connector Board Unplug the (a) LCD cover switch cable (CN8) and (b) speaker cables (CN7 and CN10).
5. Turn the unit over and remove the two screws that secure the Charger Board to the inside of the assembly frame. Then remove the board. Figure 4-22 6. Removing the Charger Board Remove seven screws that secure the motherboard to the inside assembly frame. Then release the latch and pull up the motherboard to detach it from the inside assembly frame.
4.5.8 Disassembling the Motherboard REMOVING THE PC CARD SLOT UNIT The PC Card Connector Module is normally part of the motherboard spare part. The following removal procedure is for reference only. Figure 4-24 Removing the PC Card Slot Unit REMOVING THE KEYBOARD CONNECTION BOARD Pull up the keyboard connection board to remove it.
4.5.9 Removing the Touchpad The touchpad is connected to the top cover. assembly: Follow these steps to remove the touchpad 1. Peel off the mylar. 2. Remove the three screws and disconnect the touchpad cable (J2), then remove the touchpad main sensor and connector unit. 3. Lift up and remove the touchpad. 4. Lift up and remove the touchpad buttons.
4.6 Disassembling the Display Follow these steps to disassemble the display: 1. Remove the oval LCD bumpers at the top of the display and the long bumper on the LCD hinge. Figure 4-27 2. Removing the LCD Bumpers Remove five screws on the display bezel. or Screw List: x4, M2.5L6 x1, M2.5L6(for 11.3” TFT LCD) x1, M2.5x8(for 11.3” STN and 12.1” TFT LCD) Screw List: x4, M2.5L6 x1, M2.5L6(for TFT LCD) x1, M2.
3. Pull out and remove the display bezel by first pulling on the inside of the bezel sides and lower bezel area. Then pull up the top bezel area. 2 1 2 1 Figure 4-29 4. 3 1 Removing the Display Bezel Twist (1), then slide out (2) and remove the Hinge Cable Cover. Figure 4-30 Removing the Hinge Cable Cover The hinge cable cover cannot be removed unless the LCD bezel is removed.
5. Remove screws on the four sides of the display panel. Then gently fold back the foil around the display panel and unplug the inverter cable (J2). The encircled screw doesn’t exist in STN LCD model . Figure 4-31 6. Removing the LCD Panel Tilt the LCD Panel away for the display cover. Then unplug the LCD Panel from the Display Cable Assembly.
5. Remove the screws that secure the DC-AC Inverter Board to the display back cover and remove the inverter boards. Then unplug the display cable. Figure 4-33 5. Removing the DC-AC Inverter and LCD ID Inverter Boards Remove five screws that secure the LCD cable to the display back over, then remove the LCD cable assembly. Screw list: x1, M2L4 x4, M2.
A p p e n d i x A Model Number Definition This appendix shows the model number definition of the notebook. 610XX-X X X Keyboard Language Version 0: Swiss/US 1: US(110V) 2: US(220V) 3: US w/o power cord 4: US K/B w/o power cord(ACLA) 5: US(110V for AAB) 6: US(220V)with CCIB for P.R.
370PXX-X X X Hard Disk 0: No Hard Disk 1: 120MB 2: 200MB B: 250MB 3:340MB 5:520MB 8:810MB 9:1.3GB A: 1GB C:1.35GB D:1.4GB E: 2.1GB LCD C :11.3" DSTN CX:11.3" TFT DX:12.
A p p e n d i x B Exploded View Diagram This appendix shows an exploded view diagram of the notebook.
B-2 Service Guide
Exploded View Diagram B-3
A p p e n d i x C Spare Parts This appendix lists the spare parts of the notebook TI EXTENSA 610. Table C-1 Spare Parts List PART NAME ACER P/N TI P/N Ref. COMMENTS Exploded View 1 IC CHARGE (power supply charger bd) 05.62062.020 9811768-0001 56 2 FAN 5V UDQFC3E09 105MM 23.10029.011 9811769-0001 32 3 ADT (AC Adapter w/o power cord) 25.10052.001 9811770-0001 4 HEAT SINK-U(2) AL AN370 34.46925.001 981177100001 30 5 CASE UPPER (TOP) 370P/TI 39.46901.031 9811772-0001 21 w/o label 6 C.
Table C1 Spare parts list (continued) PART NAME ACER P/N TI P/N Ref. COMMENTS Exploded View 1 HINGE (L), SAE AN370, EXT 61X 34.46909.001 9813520-0001 2 HINGE ( R), EXT. 61X 34.46905.001 9811814-0001 3 MYLAR, LCD, 100MM, EXT 61X 40.46928.001 9811817-0001 4 LCD LATCH, EXT 61X 6M.48410.001 9815579-0001 3, 4 1 INVERTER T62.064.C.00 370P 19.21030.101 9811790-0001 12 3 C.A 31P FPC 11.3"STN 370(W.C) 6M.48412.001 9811791-0001 1,2 4 (LCD PANEL) LCDM LMG9900 11.
Table C1 Spare parts list (continued) PART NAME ACER P/N TI P/N Ref. COMMENTS Exploded View << MAIN BD >> 1 IC CPU INTEL P54CSLM 120M 3.1V 01.IP54S.C0M 9811798-0001 2 IC CPU INTEL P54CSLM 150M 2.9V SPGA 01.IP54S.F0B 9815594-0001 01.ip55c.f00 9815595-0001 4 MAIN BOARD 0MB W/O CPU 370P 55.48401.001 9811800-0001 w/o CPU 5 AUDIO BOARD 370P 6M.48417.001 9811801-0001 31 audio bd & cable 6 HDD TRANSFER BOARD 370P 55.48403.
Table C1 Spare parts list (continued) PART NAME ACER P/N TI P/N Ref. COMMENTS Exploded View KB-84 KEY KAS1901-0161R US 370 (US) 90.46907.001 9805728-0001 27 w/cable Keyboard(UK) 90.46907.00U 9805758-0002 27 w/cable Keyboard(Germany) 90.46907.00G 9805758-0003 27 w/cable Keyboard(French) 90.46907.00F 9805758-0004 27 w/cable Keyboard(Spanish) 90.46907.00S 9805758-0005 27 w/cable Keyboard(Sws/Ger) 90.46907.007 9805758-0006 27 w/cable Keyboard(Italian) 90.46907.
Table C1 Spare parts list (continued) PART NAME ACER P/N TI P/N 6M.48409.001 9815599-0001 Ref. COMMENTS Exploded View SERVICE KITS MISC. PARTS PACK 1 2 3 4 5 6 SCREW LCD CAP(47.46901.001) * 10 PCS CLIPPER CABLE(42.46921.001) * 10 PCS RUBBER FOOT (47.46902.001) * 10 PCS FOOT PU BLACK (47.45001.001)*10 PCS CD LATCH(42.46903.001) * 10 PCS SCREW PACK 1 2 3 4 5 6 7 8 9 6M.48419.001 M2L4(86.1A352.4R0) * 10 PCS M2L14(86.1A522.140) * 10 PCS M2.5L5(86.4A553.5R0) * 10 PCS M2.5L6(BLACK)(86.1AI23.
Table C1 Spare parts list (continued) PART NAME options Misc. ACER P/N TI P/N EXT BTY CHARGER 91.48428.001 370P ONLY 91.48428.001 9811764-0001 EXT FLOPPY DRIVE 91.46905.002 370/370P 91.46905.002 9811765-0001 PS/2 CABLE 50.46812.001 50.46812.001 9811766-0001 FILE TRANSFER CABLE 50.30014.001 50.30014.001 9811767-0001 AC ADAPTER ASSY,EXTENSA 61X w/power cord 91.48428.011 9811754-0001 BATTERY PACK,EXTENSA 61X,NIMH SANYO 91.46928.012 9811738-0001 BATTERY PACK,EXTENSA 61X,NIMH TOSHIBA 91.
A p p e n d i x Schematics This appendix shows the schematic diagrams of the notebook.
3.3V 2.9V 3.3V 2 2,5 $CPUA[3..31] $CPUA3 $CPUA4 $CPUA5 $CPUA6 $CPUA7 $CPUA8 $CPUA9 $CPUA10 $CPUA11 $CPUA12 $CPUA13 $CPUA14 $CPUA15 $CPUA16 $CPUA17 $CPUA18 $CPUA19 $CPUA20 $CPUA21 $CPUA22 $CPUA23 $CPUA24 $CPUA25 $CPUA26 $CPUA27 $CPUA28 $CPUA29 $CPUA30 $CPUA31 $BE#0 $BE#1 $BE#2 $BE#3 $BE#4 $BE#5 $BE#6 $BE#7 4 $A20M# $BE#[0..7] $BE#[0..7] R102 NOT INSTALL INSTALL:M1 NIS:P54C/K5 3.3V R102 1 2 3.
+5V 8 8 8 1,5 $CPUD[0..63] TH_DQ TH_CLK TH_RST# U22 DQ CLK/CONV# RST# GND DS1620 1 2 3 4 $CPUD[0..
3.3V 6 MD[0..63] MD[0..
3.3V 8 $23STP# $1523INTR 1 $IGNNE# 1 $A20M# 1 $FERR# 1,24 $CPURST 13 EXTSW# 1 $NMI 23 PWRGOOD 7 $ALA14M 8 IRQ8# SIRQI 1 R12 10KR3 2 2 3 U S B C K +5V 3.
## ADD CX1,CX2,CX7,CX8,CX9 1 $BE#[0..7] 3.3V 3.3V CX9 SCD1U CX1 SCD1U 4 1 6 9 1 2 2 5 6 7 7 1 5 5 1 4 1 0 7 4 1 0 7 $CADV# $CPUADS# $CADS# $L2CLK2 $CCS# CS2 7 $L2CLK2 2 $CPUA[3..
3.3V 3.3V CN21 145 3.3V MD0 MD1 MD2 MD3 C271 SC4D7U16V6ZY C225 SCD1U C261 SC4D7U16V6ZY C186 SCD1U C224 SCD1U C234 SCD1U C244 SCD1U MD4 MD5 MD6 MD7 MA[2..11] 3 MA[2..11] 3 C268 SC4D7U16V6ZY 3.3V MD[0..63] MD[0..
3.3V 3.3V 1 1 R180 22KR3 R179 22KR3 3.3V 2 3.3V 2 1 SW3 1 2 3 4 8 7 6 5 FOR CY2263 1 R105 10KR3 2 2 R106 10KR3 FS1 FS0 $BF1 $BF0 $BF1 S0 S1 CLOCK $BF2 1 1 0 0 0 0 50MHZ 0 1 60MHZ 1 0 66.6MHZ 1 1 33MHZ 1 0 1 0 +5V 1.5X 2X 3X 2.5X +5V KHS04 +5V 14 2 VCC D 3 CLK KBD14M 7 3.
+5V +5V 3.3V U43C 1 4 1 4 LLED# VR_U/D# 19 BLVR# 19 $7101STP# U26B +5V 4 5 6 3.
+5V +5V 1 SB: ADD DUMMY RESISTER TO U40 PIN 22 R35 10KR3 SD[0..7] 2 23 PWRGOOD# 4 RTCAS 24 RTCRW 24 RTCDS PWRGOOD# RTCAS RTCRW RTCDS G1 1 2 GAP-OPEN 1 BT1 BH-12 U27 VCC CS$ AS R/W$ DS RST$ RCL$ EXTRAM BC X1 3 X2 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 INT$ SQW MOT VSS VSS 4,10,11,13,15 SD[0..
+5V +5V 4,9,11,13,15 +5V K C O L 1 SD[0..7] SD[0..
+5V +5V SB: CHANGE MAX213 TO MAX3243 C164 C163 12 SOUT1 RTS1# DTR1# P PP P D DD D 4 5 6 7 ACK# BUSYP PE SLCT STROB# IRQ[3..7] I I R R QQ 3 4 +5V 24 RSTDRV 4 TC 7 $P24M SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 4 IOW# 4 IOR# 4 AEN 4,9,10,13,15 I I I R R R QQQ 5 6 7 1 0 9 9 9 9 9 9 9 9 9 9 8 8 8 8 8 8 8 8 8 8 7 7 7 7 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 4,13 0WS# 4,8 DRQ2 4 DACK#2 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SD[0..
+5V FDDCHG 4 5 +5V 6 11 D7 RB731U FDDDCHG 3 2 14 INDEX# 11 DR1# EXTDR1# EXT3_MODE RP22 PAUTOFD# PERROR# PINIT# PSLCTIN# 1 2 3 4 5 10 9 8 7 6 8,14 PSLCT PPE PACK# 3_MODE 11 HDSEL EXTHDSEL EXTWDATA# WDATA# FDDRDY# 14 SRP4K7 RP21 PPD0 PPD1 PPD2 PPD3 1 2 3 4 5 PPD4 PPD5 PPD6 PPD7 EXTRDATA# 11,14 14 RDATA# TRK0# EXTTRK0# EXTWRTPRT# RP23 1 2 3 4 PPD0 PPD1 PPD2 PPD3 8 7 6 5 11,14 WRTPRT# SRN33 FDDRDY# RP24 PD4 PD5 PD6 PD7 1 2 3 4 EXTMTR1# EXTFDIR EXTSTEP# EXTWGATE# 11 DSKCHG MTR
HDD+5V HDD+5V 4,9,10,11,15 HDD+5V SD[0..
+5V HDD+5V +5V ## ADD CX3,CX4 CDROM+5V FX1 FX2 1 +5V R124 4K7R3 4 3 HDD+5V 1 2 R206 4K7R3 4 IDE_DRQ0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 IDE_D8 IDE_D9 IDE_D10 IDE_D11 IDE_D12 IDE_D13 IDE_D14 IDE_D15 IDE_IOR# IDE_RDY IDE_DACK0# IDE_A2 IDE_CS3# HDD+5V RP33 +5V FUSE-2D5A125V FX1, FX2 P/N:69.41501.
DVDD3 C68 AUX2R CX15 SCD1U CX16 SCD1U C67 SCD1U SC1U16V5JX C39 CX17 SC10U10V6JY R71 AUX2L 14 CD_AUDR 1 C216 CD_R 2 SC1U16V5JX 10KR3 1 14 CD_AUDL ## ADD CX15,CX16 R70 C75 10KR3 AVDD5 2 1 R146 7K5R5F 16 LINE_IN_R G3 C38 1 C40 SC1U16V5JX C194 SCD01U C62 C61 S Y N H L S Y N H R MLB321611 C41 1 0 9 9 9 9 9 9 9 9 9 9 8 8 8 8 8 8 8 8 8 8 7 7 7 7 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 DVDD3 AVDD5 MIN SC1U16V5ZY R53 220KR3 DVDD3 2 24 RSTDRV 4 IOW# 4 IOR# 4 AEN 4 4 4
RX2 +5V 1 1 8 LED# +5V 2 13 8 DISPLED# 5VSB_DC 1 4 23 BT_QCHG L16 AMPVCC 2 CHARGELED 2 U25C MLB321611 5VSB_DC 1 4 9 8 7 CX36 SC1U16V5JX 5VSB_DC 1 4 U25B 4 SSHC00 6 5 R7 1 5VSB_DC SSHC00 7 10 C182 SCD1U U25A 1 3 SSHC14 7 5VSB_DC 1 4 ## CIRCUIT MODIFY +5V 1 2 1 12 5VSB_DC QX1 RN1424 U38F 1 4 DISPLED LED# 2 47KR3 3 R25 22KR3 2 SSHC00 7 R24 1 SOUND_L 2 4 3 2 1 22KR3 ENAUDIO C169 SC1U25V5MY ININ+ BYPASS SHUTDOWN G N D 7 19 BBT_QCHG 13 SSHC00 7 D8 1 V
+5V 18 18 18 VMBD[0..15] 1 VAA0 VAA5 2 SRN4K7 R41 AD22 1 3,4,21 +5V CBE#[0..3] 1 R191 10KR3 2 11 33R3 FRAME# IRDY# TRDY# DEVSEL# STOP# PAR CBE#0 CBE#1 CBE#2 CBE#3 24 PCIRST# G5 2 GAP-CLOSE RGBGND 7 $VGACLK 3,21 4 PERR# SERR# 7 $G14.
VGAPWR C57 SC10U16V C55 SCD1U C56 SC1000P50V3KX LCDPWR LCD_3/5V# 0 0 1 1 ENAVDD 0 1 0 1 S1 0 1 0 0 S2 0 0 0 1 17 VMAD[0..15] VRAMVCC VGAPWR C80 SCD1U 3.3V 3.
17 17 +5V 17 R[0..
R16 1 17 R 17 G R14 2 10R3 R13 1 17 B 2 10R3 +5V 1 1 1 R19 75R3 2 1 2 1 D3 BAV99LT1 R155 17 FLM 1 2 R18 75R3 2 1 D1 BAV99LT1 3 L9 1 NL322522T-2R2 L10 1 NL322522T-2R2 L11 1 NL322522T-2R2 2 10R3 1 R17 75R3 2 19 CRT_G 19 2 CRT_B 19 C13 SC47P C12 SC47P C14 SC47P 2 D2 BAV99LT1 RGBGND 3 3 1 C204 SC33P 2 PLFS 19 PLFS R40 22R3 1 17 HSYNC L14 2 1 10R3 R165 1 CRT_R 2 R111 2 10R3 17 LP 2 2 1 10R3 C218 SC33P 2 R39 PLP 2 PLP 19 1 17 VSYNC +5V 22R3 CRT_H
3,4,8,17,21 3,4,8,17 3,4,8,17 3,4,8,17 3,4,8,17 3,4,17 3,17 3,4,8,17,21 CBE#2 FRAME# IRDY# TRDY# DEVSEL# STOP# PERR# 4 SERR# PAR CBE#1 3,4,8,17 3,4,8,17,21 A D 2 0 1 C P B A E R # 1 AD[0..31] AD[0..31] A D 1 2 3.
A_VPP A_SLOT_VCC 1 C208 SCD1U R156 100KR3 C207 SC10U16V C210 SC1000P50V3KX C203 SCD1U 21 19,21 2 SKT1 5 6 3 4 B_VPP A_D[0..15] A_D[0..15] 1 6 2 A_A[0..25] A_A[0..25] A_D3 B_SLOT_VCC 21,24 A_CD1# A_CD1# 1 2 C180 SCD1U 1 R142 100KR3 C20 SC10U16V C22 SC1000P50V3KX A_D4 A_D11 A_D5 A_D12 A_D6 A_D13 A_D7 A_D14 C21 SCD1U 2 PCM-SKT A_CE1# 21 A_CE1# A_D15 3.
## REMOVE C27,ADD CX12 CX13 CX6 ## REMOVE C69,ADD CX20,CX21 ## REMOVE C52 C51,ADD CX22,CX23 +12V ## 5VSB_DC IS PROVIDED BY CHARGER +5V +12V C70 SC1U25V5MY C54 SCD1U CX22 C53 SC10U16V SC1000P50V3KX CX12 SCD1U +12V +7V +7V C197 SC1U25V5MY CX33 SC10U16V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 DCBATOUT +7V 3.3V CX13 SCD1U 2.9V ON/OFF# PWRGIN 3.
COMMON ALADDIN III +5V R171 1 +5V 1 U41A 4 3,10,14,17,21,22 2 PCIRST# 4 $CPURST 4 PULL L: 5V suspend mode enable. R43 7 SSHCT04 1 U41B 4 RSTDRV 10KR3 4 XDIR 1 +5V 11,13,15 1 3 L: DMA DACK[7:5,3:0] polling enable. *** If L, add ALDN3 P.21 MUX! H: DMA DACK[7:5,3:0] polling disable. 4 SPLED R42 4 SPKR 8 4 IOW# SSHC00 7 4 RTCROMCS# 5VSB_DC 1 4 R38 3 RTCRW 9 4 TC 4 IOR# 7 SSHCT32 L: External I/O APIC mode supported. 2 H: Ext. I/O APIC mode not supported.
BYPASS CAPACITORS CPU 3.3V M1521 2.9V 2.9V 3.3V C238 C120 SCD1U C113 SC1000P50V3KX C251 SC2K2P 1 ST100U10VDK 1 C246 ST100U10VDK 2 2 2.9V 2.9V C240 SCD1U C213 SCD1U C232 SCD1U C245 SCD1U C36 SCD1U C247 SCD1U C206 SCD1U 1 2 C122 ST100U10VDK C248 C110 SC1U16V5ZY SCD1U CLOSE TO PIN7,9,11,13,15,17 C108 SCD1U C118 SC10U16V P/N: 80.15711.341 7343,D SIZE 3.3V CLOSE TO PIN 105,106,119 3.3V C119 SCD1U C121 C115 SC1000P50V3KX SC2K2P C127 SCD1U 3.
A p p e n d i x E BIOS POST Checkpoints This appendix lists the POST checkpoints of the notebook BIOS. Table E-1 POST Checkpoint List Description Checkpoint 04h • Check CPU ID • Dispatch Shutdown Path Note: At the beginning of POST, port 64 bit 2 (8042 system flag) is read to determine whether this POST is caused by a cold or warm boot. If it is a cold boot, a complete POST is performed. If it is a warm boot, the chip initialization and memory test is eliminated from the POST routine.
Table E-1 POST Checkpoint List (Continued) Description Checkpoint 2Ch • • 128K base memory testing Set default SS:SP= 0:400 Note: The 128K base memory area is tested for POST execution. The remaining memory area is tested later.
Table E-1 POST Checkpoint List (Continued) Checkpoint Description • Reset pointing device • Check pointing device 70h • Parallel port testing 74h • Serial port testing 78h • Math Coprocessor testing 80h • Set security status 84h • KB device initialization 7Ch • • Set KB led upon setup requests Note: If keyboard Number Lock is enabled, the NumLock LED (if present) should be turned on.
