Service manual

PDI-P23LCD SERVICE MANUAL
PAGE:
67
CIRCUIT DESCRIPTIONS
3. Video A/D Converter
Device: MST9883CR.
Features: *Triple ADC with 12 - 140 MHz Sampling Rate
*Integrated line locked PLL generates pixel clock from HSYNC
*Integrated 5-bit pixel clock phase adjustment for precise sample timing
control
*Integrated clamp with timing generator
*Integrated Brightness & Contrast controls
*Integrated precision voltage reference
*Compatible with VGA through SXGA RGB graphics signals, and component
TV, DTV and HDTV
*Pin Compatible with AD9883A
*Serial port programming interface
*Mid-Scale Clamping
*Fully Sync Processing
*4:2:2 and 4:4:4 Output Format Mode
*Color space conversion (RGB to YCbCr)
*Internal pattern generator*
*Sawtooth vertical deflection signals for VSYNC input*
*BT656 output format mode*
*Black and mid-level precision clamp and calibration*
*Please see MST9883C Application Note for details.RGB Graphics
Processing
(A/D Converter).
1) Description
Most flat-panel monitors and projectors require a digital graphics input in order to accurately
scale and display
graphics. The huge installed base of computers with analog video graphics interfaces
necessitates the use of a
graphics digitizer to re-digitize the analog RGB signal before further processing.
■The MST9883CR is a fully integrated analog interface for digitizing high-resolution RGB
graphics signals from PC’s and workstations. With a sampling rate capability of up to 140
MHz, it can accurately support display resolutions up to 1280x1024 (SXGA) at 75 Hz. The
clamped input circuits provide sufficient band width to accurately digitize each pixel.
■The MST9883CR provides a high performance highly integrated solution to support the
digitization process, including the ADC’s, a voltage reference, a PLL to generate the pixel
sampling clock from HSYNC, clamping circuits, and programmable offset and gain
circuits to provide brightness and contrast controls.
■When the COAST signal is asserted, the PLL will maintain its output frequency when
HSYNC pulses are absent, such as during the VSYNC period in some systems.
■A 32-step programmable phase adjustment control (0-360 deg) is provided for the pixel
sampling clock to adjust for the difference between the HSYNC edge and RGB pixel edge timing.
■The MST9883CR can send output data through one 24-bit port at the pixel clock rate.
■The MST9883CR can also support RGB to YCbCr conversion.
■The MST9883CR has internal programmable pattern generator for testing.
■The MST9883CR can accept either standard TTL, CMOS levels or sawtooth vertical
deflection signals for VSYNC input.