User's Manual

84 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 2: Input/Output Interfaces
R
is transferred from the DCU to the PLB slave. If this signal is deasserted, valid data on the
write data bus has not been latched by the PLB slave.
Write-data acknowledgement is asserted for one cycle per transfer. There is no limit to the
number of cycles between two transfers. The number of transfers (and the number of
write-data acknowledgements) depends on the PLB slave size (specified by
PLBC405DCUSSIZE1 and the line-transfer size (specified by C405PLBDCUSIZE2). The
number of transfers are summarized as follows:
x Single word writes require one transfer, regardless of the PLB slave size.
x Eight-word line writes require eight transfers when sent to a 32-bit PLB slave.
x Eight-word line writes require four transfers when sent to a 64-bit PLB slave.
PLBC405DCUBUSY (Input)
When asserted, this signal indicates the PLB slave acknowledged and is responding to (is
busy with) a DCU data-access request. When deasserted, the PLB slave is not responding
to a DCU data-access request.
This signal should be asserted in the cycle after a DCU request is acknowledged by the PLB
slave and remain asserted until the request is completed by the PLB slave. For read
requests, it should be deasserted in the cycle after the last read-data acknowledgement. For
write requests, it should be deasserted in the cycle after the target memory device is
updated by the PLB slave. If multiple requests are initiated and overlap, the busy signal
should be asserted in the cycle after the first request is acknowledged and remain asserted
until the cycle after the last request is completed.
The processor monitors the busy signal when executing a sync instruction. The sync
instruction requires that all storage operations initiated prior to the sync be completed
before subsequent instructions are executed. Storage operations are considered complete
when there are no pending DCU requests and the busy signal is deasserted.
Following reset, the processor block prevents the DCU from accessing data until the busy
signal is deasserted for the first time. This is useful in situations where the processor block
is reset by a core reset, but PLB devices are not reset. Waiting for the busy signal to be
deasserted prevents data accesses following reset from interfering with PLB activity that
was initiated before reset.
PLBC405DCUERR (Input)
When asserted, this signal indicates the PLB slave detected an error when attempting to
transfer data to or from the DCU. The error signal should be asserted for only one cycle.
When deasserted, no error is detected.
For read operations, this signal should be asserted with the read-data acknowledgement
signal that corresponds to the erroneous transfer. For write operations, it is possible for the
error to not be detected until some time after the data is accepted by the PLB slave. Thus,
the signal can be asserted independently of the write-data acknowledgement signal that
corresponds to the erroneous transfer. However, it must be asserted while the busy signal
is asserted.
The PLB slave must not terminate data transfers when an error is detected. The processor
block is responsible for responding to any error detected by the PLB slave. A machine-
check exception occurs if the exception is enabled by software (MSR[ME]
1) and data is
transferred between the processor block and a PLB slave while the error signal is asserted.