User's Manual
188 www.xilinx.com PowerPC™ 405 Processor Block Reference Guide
1-800-255-7778 UG018 (v2.0) August 20, 2004
Chapter 4: PowerPC 405 APU Controller
R
The decoded instructions require an FCM floating point unit to be used. FPU instructions
that return results to the PowerPC will default to execute as non-autonomous, non-
blocking. All other FPU instructions default to execute as autonomous. The user can force
FPU instructions to be non-blocking in an APU Controller configuration register.
Note: While the APU controller decodes these instructions, the FCM has to decode them
independently for its own execution. The APU can send the 32-bit instruction, but it cannot tell the
FCM which FPU instruction it decoded.
FCM Load/Store Instructions
FCM Load/Store instructions transfer data between the PowerPC’s data memory system
(D-Cache or DSPLB/DSOCM addressable memory) and the Fabric Co-processor Module
(FCM). An FCM Load transfers data from a memory location to a destination register in the
FCM and vice-versa for an FCM Store. All Load/Store instructions are of indexed format,
that is, RA stores the base address and RB the offset.
FCM Load/Store should not be confused with user-defined FCM read/write instructions.
A user-defined FCM read that transfers data from the PowerPC to the FCM will access data
from the PowerPC GPR operand registers not from DSOCM or DSPLB memory. The same
is true for a user-defined FCM write instruction.
The FCM Load and Store instructions behave somewhat differently in comparison with
other FCM instructions. In a way, they are semi-autonomous because the PowerPC CPU is
responsible for performing the necessary memory access involved. That is, the processor
pipeline is executing, but it is executing a memory access related to the Load/Store
instruction. Since FCM Store instructions can be flushed by the processor, the APU
Controller is responsible for signalling the FCM when it is safe to commit internal state
changes.
For details regarding instruction flushing refer to the “FCM Instruction Flushing” section
of this chapter.
Note: While the APU controller decodes Load/Store instructions, the FCM has to decode them
independently for its own execution. The APU can send the 32-bit instruction, but it cannot tell the
FCM which FPU instruction it decoded.
x
fdiv
x
fdiv.
x
fdivs
x
fdivs.
x
fsqrt
x
fsqrt.
x
fsqrts
x
fsqrts.
x
fcfid
x
fctid
x
fctidz
x
fctiw
x
fctiw.
x
fctiwz
x
fctiwz.
Complex Arithmetic Group
Conversion Group
x
fres
x
fres.
x
frsqrte
x
frsqrte.
Estimates Group