User's Manual

PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 17
UG018 (v2.0) August 20, 2004 1-800-255-7778
R
Chapter 1
Introduction to the
PowerPC 405 Processor
The PowerPC 405 is a 32-bit implementation of the PowerPC embedded-environment
architecture that is derived from the PowerPC architecture. Specifically, the PowerPC 405 is
an embedded PowerPC 405D5 (for Virtex-II Pro) or 405F6 (for Virtex-4) processor core. The
term processor block is used throughout this document to refer to the combination of a
PPC405D5 or PPC405F6 core, on-chip memory logic (OCM), an APU controller (Virtex-4
only), and the gasket logic and interface.
The PowerPC architecture provides a software model that ensures compatibility between
implementations of the PowerPC family of microprocessors. The PowerPC architecture
defines parameters that guarantee compatible processor implementations at the
application-program level, allowing broad flexibility in the development of derivative
PowerPC implementations that meet specific market requirements.
This chapter provides an overview of the PowerPC architecture and an introduction to the
features of the PowerPC 405 core. The following topics are included:
x “PowerPC Architecture”
x “PowerPC 405 Software Features”
x “PowerPC 405 Hardware Organization”
x “PowerPC 405 Performance”
PowerPC Architecture
The PowerPC architecture is a 64-bit architecture with a 32-bit subset. The various features
of the PowerPC architecture are defined at three levels. This layering provides flexibility
by allowing degrees of software compatibility across a wide range of implementations. For
example, an implementation such as an embedded controller can support the user
instruction set, but not the memory management, exception, and cache models where it
might be impractical to do so.
The three levels of the PowerPC architecture are defined in Table 1-1.