User's Manual

PowerPC™ 405 Processor Block Reference Guide www.xilinx.com 129
UG018 (v2.0) August 20, 2004 1-800-255-7778
R
Debug Interface I/O Signal Descriptions
The following sections describe the operation of the debug interface I/O signals.
DBGC405EXTBUSHOLDACK (Input)
When asserted, this signal indicates that the bus controller (for example, a PLB arbiter) has
given control of the bus to an external master. When deasserted, an external master does
not have control of the bus. This signal is used by the PowerPC 405 debug logic (and the
external debugger) as an indication that the processor might not have control of the bus
and therefore might not be able to respond immediately to certain debug operations.
External FPGA logic generates this signal using output signals from the bus controller.
DBGC405DEBUGHALT (Input)
When asserted, this signal stops the processor from fetching and executing instructions so
that an external debug tool can operate the processor. From this state, known as debug halt
mode, an external debugger controls the processor using the JTAG interface and the private
JTAG hardware debug instructions. The clocks are not stopped. When this signal is
deasserted, the processor operates normally.
This signal enables an external debugger to stop the processor without using the JTAG
interface. A stop command issued through the JTAG interface (using a private JTAG
instruction) is discarded when the processor is reset. The debug halt signal can be asserted
during a reset so that the processor is stopped at the first instruction to be executed when
reset is exited.
Table 2-26: Debug Interface I/O Signals
Signal
I/O
Type
If Unused Function
DBGC405EXTBUSHOLDACK I 0 Indicates the bus controller has given control of
the bus to an external master.
DBGC405DEBUGHALT I 0 Indicates the external debug logic is placing the
processor in debug halt mode.
DBGC405UNCONDDEBUGEVENT I 0 Indicates the external debug logic is causing an
unconditional debug event.
C405DBGWBFULL O No Connect Indicates the PowerPC 405 writeback pipeline
stage is full.
C405DBGWBIAR[0:29] O No Connect The address of the current instruction in the
PowerPC 405 writeback pipeline stage.
C405DBGWBCOMPLETE O No Connect Indicates the current instruction in the PowerPC
405 writeback pipeline stage is completing.
C405DBGMSRWE O No Connect Indicates the value of MSR[WE].
C405DBGSTOPACK O No Connect Indicates the PowerPC 405 is in debug halt mode.
C405DBGLOADDATAONAPUDBUS O No Connect Virtex-4-FX only. Valid load data transferred
between the APU controller and PowerPC 405
core.