User's Manual
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Table Of Contents
LogiCORE™ PCI v3.0
About This Guide
Guide Contents
Additional Resources
Conventions
Typographical
Online Document
Getting Started
About the Example Design
Additional Documentation
Technical Support
Feedback
PCI Interface Core
Document
Installing and Licensing the Core
System Requirements
Installing the Core
CORE Generator IP Updates Installer
Manual Installation: CORE Generator IP Update
Direct Download of Standalone Core
Licensing Options
Evaluation
Full
Direct Download
Installing Your License File
Family Specific Considerations
Design Support
Device Initialization
Bus Width Detection
Datapath Output Clock Enable
Input Delay Buffers
Regional Clock Usage
Bus Clock Usage
Electrical Compliance
Generating Bitstreams
Functional Simulation
Cadence NC-Verilog
Model Technology ModelSim
Verilog
VHDL
Synthesizing a Design
Synplicity Synplify
Verilog
VHDL
Exemplar LeonardoSpectrum
Xilinx XST
Implementing a Design
ISE Foundation
Timing Simulation
Cadence NC-Verilog
Model Technology ModelSim
Verilog
VHDL
PCI v3.0.151 Ge
tting Started Guide
www
.xilinx.com
UG157 August 31, 2005
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