User manual

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 35
UG154 March 24, 2008
Demonstration Test Bench
R
• Status Monitor
• Testcase
Clock Generator
The Clock Generator creates all of the clocks that are used in the Design Example,
including
SysClk, RDClk2x, UserClk, TSClk, and SnkIdelayRefClk. These clocks are
described in more detail in Table 4-10.
Figure 4-3: Test Bench Modules
Demonstration Testbench
Testcase
Module
Stimulus
Module
Static Config. Signals
TCDat
TCCtl
TCStat
TCChan
TCIdleRequest
TCTrainingRequest
TCSinkDip2ErrRequest
TCDIP2Request
CtlFull
FFWriteEn
SopErr
GetStatusChan
GetStatus
FullVec
Status
Monitor
SnkInFrame
Data
Monitor
SrcInFrame
Procedures
Testcase
Package
Clock
Generator