User manual

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 33
UG154 March 24, 2008
Example Design Configuration
R
connects to a SPI-4.2 PHY layer device or network processor. Figure 4-1 shows the example
design modules architecture and interfaces to the SPI-4.2 core.
Loopback Module
The Loopback Module connects to the user interface of the SPI-4.2 Sink and Source cores.
There is a Read Module that accesses packet data from the Sink FIFO and a Write Module
that transfers data into the Source FIFO. The Read Module polls the status signals
SnkFFEmpty_n and SnkFFAlmostEmpty_n to determine whether it can perform a read
from the Sink FIFO. The Write Module polls SrcFFAlmostFull_n to determine whether
it can transfer data into the Source FIFO.
Basic Loopback Operation
When the Almost Full flag (SrcFFAlmostFull_n) is deasserted, the Write Module
asserts a read request (RReq) that is sent to the Read Module. When a read request is
received, the Read Module verifies that the FIFO is not empty and initiates a read from the
Sink FIFO. On the next cycle, the data appears on SnkFFData, and SnkFFValid is
asserted. SnkFFValid drives the SrcFFWrEn_n signal directly, which enables the writing
of data into the Source FIFO. The transfer of data continues until the Source FIFO becomes
almost full or the Sink FIFO becomes empty. If the Source FIFO becomes almost full, all
outstanding data is written into the Source FIFO and the transfer of data between the
FIFOs is halted.
Figure 4-1: Example Design Configuration
SPI-4.2 CoreLoopBack Module
Sink
Interface
PL4
Source
Interface
Write Module
Read Module
SnkFFData
SnkFFAddr
SnkFFMod
SnkFFSOP
SnkFFEOP
SnkFFErr
SrcFFData
SrcFFAddr
SrcFFMod
SrcFFSOP
SrcFFEOP
SrcFFErr
SrcFFWrEn_n
SrcFFAlmostFull_n
SnkFFValid
Write
State
Machine
SnkFFAlmostEmpty_n
SnkFFEmpty_n
SnkFFRdEn_n
Read
State
Machine
Register
Bank
RAck
RReq