User manual

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 27
UG154 March 24, 2008
Directory and File Contents
R
<component name>/example design
The example design directory contains the example design files provided with the core.
spi4_2_ug153.pdf
SPI-4.2 User Guide
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Table 4-3: Doc Directory (Continued)
Name Description
Table 4-4: Example Design Directory
Name Description
<project_dir>/<component_name>/example_design
<component_name>_top.ucf
User constraints file (UCF) provides
example constraints necessary for
processing the core using Xilinx
implementation tools. This file can be
modified to meet individual system
requirements. The example UCF contains
timing and placement constraints for both
Sink and Source cores.
<component_name>_top.v[hd]
VHDL or Verilog wrapper file for the
example design; it instantiates the Sink and
Source cores and the loopback module.
This is the top-level synthesis file for the
example design.
pl4_fifo_loopback.v[hd]
Top-level loopback file used in the example
design; it instantiates the loopback read
and write modules.
pl4_fifo_loopback_read.v[hd]
Loopback read module used in the
example design; it interfaces to the SPI-4.2
Sink core.
pl4_fifo_loopback_write.v[hd]
Loopback write module used in the
example design; it interfaces to the SPI-4.2
Source core.
pl4_src_clk.v[hd]
Example clocking module used in the
example design when the Source core is
configured for slave clocking.
virtex4.v
Module instantiation for Virtex-4
primitives
virtex5.v
Module instantiation for Virtex-5
primitives
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