User manual

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 21

UG154 March 24, 2008

Implementing the Example Design

After generating a core with a Full System Hardware Evaluation or Full license, the netlists

and the example design can be processed by the Xilinx implementation tools. The

generated output files include scripts to assist you in running the Xilinx tools.

To implement the SPI-4.2 example design, open a command prompt or terminal window

and type the following commands:

For Windows

ms-dos> cd <proj>\<quickstart>\implement

ms-dos> implement.bat

For Linux

% cd <proj>/<quickstart>/implement

% ./implement.sh

These commands execute a script that synthesizes, builds, maps, and place-and-routes the

example design. The script then generates a post-par simulation model for use in timing

simulation. The resulting files are placed in the results directory.

Running the Simulation

Using the provided example design, you can quickly simulate and observe the behavior of

the SPI-4.2 core. There are two different simulation types, functional and timing. The

simulation models provided are either in VHDL or Verilog, depending on the CORE

Generator Design Entry project option selected by the user.

Setting up for Simulation

The Xilinx UniSim and SimPrim libraries must be mapped into the simulator. If the UniSim

or SimPrim libraries are not set for the test environment, go to www.xilinx.com/support

where the following solution records are located:

• Compiling Xilinx Simulation Libraries (MTI) - Answer Record 2561

• Compiling Xilinx Simulation Libraries (NC-SIM) - Answer Record 2554

Functional Simulation

Instructions for running a functional simulation of the SPI-4.2 core using either VHDL or

Verilog are given below. Functional simulation models are provided when the core is

generated. Note that implementing the core before simulating the functional models is not

required. If a configuration file (referenced in the CORE Generator GUI as the COE file)

was used to program the calendar, special steps are required to include the calendar

sequence in the simulation. See the SPI-4.2 Core User Guide for details on including the

calendar initialization values in simulation.

To run a VHDL or Verilog functional simulation of the example design using MTI:

1. Set the current directory to:

<quickstart>/simulation/functional/

2. Launch the ModelSim® simulator.

3. Launch the simulation script:

modelsim> do simulate_mti.do