User manual

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 15
UG154 March 24, 2008
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Chapter 2
Licensing the Core
This chapter provides instructions for obtaining a license for the core so that you can use
the core in a design. The SPI-4.2 core is provided under the terms of the Xilinx LogiCORE
Site License Agreement. This license agreement conforms to the terms of the SignOnce IP
License standard defined by the Common License Consortium. Purchase of the core
entitles you to technical support and access to updates for a period of one year.
Before you Begin
This chapter assumes that you have installed the core using either the CORE Generator
TM
IP Update installer or by performing a manual installation after downloading the core
from the web. For information about installing the core, see the SPI-4.2 product page
.
Before installing the core, you must have a Xilinx.com account and the ISE 10.1 software
installed on your system.
To set up an account and install the ISE software:
1. Click Sign in to Access Account at the top of the Xilinx home page
; then follow the
instructions to create a support account.
2. Install the ISE 10.1 software with the applicable service pack.
License Options
The SPI-4.2 core provides three licensing options, described below.
Simulation-Only Evaluation
The Simulation-Only Evaluation license is provided with the Xilinx CORE Generator
system. This license lets you evaluate core functionality using a provided example design.
You can also use your own design and simulate the various interfaces on the core.
Functional simulation is supported by a dynamically generated gate-level netlist.
Full System Hardware Evaluation
The Full System Hardware Evaluation license is available at no cost and lets you fully
integrate the core into an FPGA design, place and route the design, evaluate timing, and
perform back-annotated gate-level simulation using the demonstration test bench
provided.
In addition, the license lets you generate a bitstream from the placed and routed design,
which can then be downloaded to a supported device and tested in hardware. The core can