User manual

SPI-4.2 v8.5 Getting Started Guide www.xilinx.com 13
UG154 March 24, 2008
R
Chapter 1
Introduction
The LogiCORE IP SPI-4.2 (PL4) core is a fully verified design solution that supports Verilog
and VHDL. The example design in this guide is provided in both Verilog and VHDL.
This chapter introduces the SPI-4.2 core and provides related information, including
recommended design experience, additional resources, technical support, and how to
submit feedback to Xilinx.
System Requirements
Windows
• Windows XP® Professional 32-bit/64-bit
• Windows Vista® Business 32-bit/64-bit
Linux
• Red Hat® Enterprise Linux WS v4.0 32-bit/64-bit
• Red Hat® Enterprise Desktop v5.0 32-bit/64-bit
(with Workstation Option)
• SUSE Linux Enterprise (SLE) v10.1 32-bit/64-bit
Software
• ISE™ 10.1 with applicable service pack
Check the release notes for the required service pack; I
SE Service Packs can be downloaded
from www.xilinx.com/xlnx/xil_sw_updates_home.jsp?update=sp
.
About the Core
The SPI-4.2 core is a Xilinx CORE Generator™ IP core, included in the latest IP update on
the Xilinx IP Center. For detailed information about the core, see the SPI-4.2 product page
.
For information about system requirements, installation, and licensing options, see
Chapter 2, “Licensing the Core.”
Recommended Design Experience
Although the SPI-4.2 core is a fully verified solution, the challenge associated with
implementing a complete design varies, depending on desired configuration and
functionality. For best results, previous experience building high-performance, pipelined
FPGA designs using Xilinx implementation software and user constraints files (UCF) is
recommended.