MicroBlaze Development Kit Spartan-3E 1600E Edition User Guide UG257 (v1.
R Xilinx is disclosing this Document and Intellectual Property (hereinafter “the Design”) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx.
Table of Contents Preface: About This Guide Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R UCF Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Clock Period Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Chapter 9: Digital to Analog Converter (DAC) SPI Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Interface Signals . . . . . . . . . . . . . . . . . . . . .
R Creating an SPI Serial Flash PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Downloading the Design to SPI Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Downloading the SPI Flash using XSPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Additional Design Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Chapter 17: DS2432 1-Wire SHA-1 EEPROM UCF Location Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 Related Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
R 6 www.xilinx.com MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.
R Preface About This Guide This user guide provides basic information on the MicroBlaze Development Kit board capabilities, functions, and design. It includes general information on how to use the various peripheral functions included on the board. For detailed reference designs, including VHDL or Verilog source code, please visit the following web link. x Spartan™-3E Starter Kit Board Reference Page http://www.xilinx.
Preface: About This Guide R x Chapter 5, “Character LCD Screen,” describes the functionality of the character LCD screen. x Chapter 6, “VGA Display Port,” describes the functionality of the VGA port. x Chapter 7, “RS-232 Serial Ports,” describes the functionality of the RS-232 serial ports. x Chapter 8, “PS/2 Mouse/Keyboard Port,” describes the functionality of the PS/2 mouse and keyboard port. x Chapter 9, “Digital to Analog Converter (DAC),” describes the functionality of the DAC.
R Chapter 1 Introduction and Overview Thank you for purchasing the Xilinx MicroBlaze™ Development Kit Spartan™-3E 1600E Edition. You will find it useful in developing your Spartan-3E FPGA application. Choose the Starter Kit Board for Your Needs Depending on specific requirements, choose the Xilinx development board that best suits your needs.
Chapter 1: Introduction and Overview x R http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=DOML403-EDK-ISE Also consider the capable boards offered by Xilinx partners: x http://www.xilinx.com/products/devboards/index.
Design Trade-Offs R x 8-pin DIP socket for auxiliary clock oscillator Design Trade-Offs A few system-level design trade-offs were required in order to provide the MicroBlaze Development Kit board with the most functionality. Configuration Methods Galore! A typical FPGA application uses a single non-volatile memory to store configuration images.
Chapter 1: Introduction and Overview 12 www.xilinx.com R MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.
R Chapter 2 Switches, Buttons, and Knob Slide Switches Locations and Labels The MicroBlaze Development Kit board has four slide switches, as shown in Figure 2-1. The slide switches are located in the lower right corner of the board and are labeled SW3 through SW0. Switch SW3 is the left-most switch, and SW0 is the right-most switch.
Chapter 2: Switches, Buttons, and Knob NET NET NET NET R "SW<0>" "SW<1>" "SW<2>" "SW<3>" LOC LOC LOC LOC = = = = "L13" "L14" "H18" "N17" | | | | IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD = = = = LVTTL LVTTL LVTTL LVTTL | | | | PULLUP PULLUP PULLUP PULLUP ; ; ; ; UG257_02_060206 Figure 2-2: UCF Constraints for Slide Switches Push-Button Switches Locations and Labels The MicroBlaze Development Kit board has four momentary-contact push-button switches, shown in Figure 2-3.
Rotary Push-Button Switch R 3.3V FPGA I/O Pin Push Button BTN_* Signal UG227_02_04_060206 Figure 2-4: Push-Button Switches Require an Internal Pull-Down Resistor in FPGA Input Pin In some applications, the BTN_SOUTH push-button switch is also a soft reset that selectively resets functions within the FPGA.
Chapter 2: Switches, Buttons, and Knob R Rotary / Push Button FPGA I/O Pin 3.3V ROT_CENTER Signal UG257_02_06_060906 Figure 2-6: Push-Button Switches Require Internal Pull-up Resistor in FPGA Input Pin Rotary Shaft Encoder In principal, the rotary shaft encoder behaves much like a cam, connected to central shaft. Rotating the shaft then operates two push-button switches, as shown in Figure 2-7. Depending on which way the shaft is rotated, one of the switches opens before the other.
Discrete LEDs R Rising edge on ‘A’ when ‘B’ is Low indicates RIGHT (clockwise) rotation Switch opening chatter on ‘A’ injects false “clicks” to the RIGHT Rotating RIGHT Detent Detent A B Switch closing chatter on ‘B’ injects false “clicks” to the LEFT (’B’ rising edge when ‘A’ is Low) Figure 2-8: UG257_02_08_060206 Outputs from Rotary Shaft Encoder May Include Mechanical Chatter UCF Location Constraints Figure 2-9 provides the UCF constraints for the four push-button switches, including the I/O
Chapter 2: Switches, Buttons, and Knob Spartan-3E Development Board LED0 LED7 R UG257_02_10_061306 Figure 2-10: Eight Discrete LEDs Operation Each LED has one side connected to ground and the other side connected to a pin on the Spartan-3E device via a 390: current limiting resistor. To light an individual LED, drive the associated FPGA control signal High.
R Chapter 3 Clock Sources Overview As shown in Figure 3-1, the MicroBlaze Development Kit board supports three primary clock input sources, all of which are located below the Xilinx logo, near the Spartan-3E logo. x The board includes an on-board 50 MHz clock oscillator. x The user clock socket is populated with a 66 MHz oscillator x Clocks can be supplied off-board via an SMA-style connector. Alternatively, the FPGA can generate clock signals or other high-speed signals on the SMA-style connector.
Chapter 3: Clock Sources R Clock Connections Each of the clock inputs connect directly to a global buffer input in I/O Bank 0, along the top of the FPGA. As shown in Table 3-1, each of the clock inputs also optimally connects to an associated DCM.
Related Resources R Location Figure 3-2 provides the UCF constraints for the three clock input sources, including the I/O pin assignment and the I/O standard used. The settings assume that jumper JP9 is set for 3.3V. If JP9 is set for 2.5V, adjust the IOSTANDARD settings accordingly.
Chapter 3: Clock Sources 22 www.xilinx.com R MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.
R Chapter 4 FPGA Configuration Options The MicroBlaze Development Kit board supports a variety of FPGA configuration options: x Download FPGA designs directly to the Spartan-3E FPGA via JTAG, using the onboard USB interface. The on-board USB-JTAG logic also provides in-system programming for the on-board Platform Flash PROM and the Xilinx XC2C64A CPLD. SPI serial Flash and StrataFlash programming are performed separately.
Chapter 4: FPGA Configuration Options R 16 Mbit ST Micro SPI Serial Flash Uses Peripheral Interface (SPI) Mode USB-based Download and Debug Port Uses standard USB cable Configuration Options PROG_B button, Platform Flash PROM, mode pins 128 Mbit Intel StrataFlash Parallel NOR Flash Memory Byte Peripheral Interface (BPI) mode UG257_04_01_061306 Figure 4-1: MicroBlaze Development Kit Board FPGA Configuration Options Configuration Mode Jumper Settings (Header J30) DONE Pin LED Lights up when FPGA success
Configuration Mode Jumpers R The configuration mode jumpers determine which configuration mode the FPGA uses when power is first applied, or whenever the PROG button is pressed. The DONE pin LED lights when the FPGA successfully finishes configuration. Pressing the PROG button forces the FPGA to restart its configuration process. The 4 Mbit Xilinx Platform Flash PROM provides easy, JTAG-programmable configuration storage for the FPGA. The FPGA configures from the Platform Flash using Master Serial mode.
Chapter 4: FPGA Configuration Options Table 4-1: R MicroBlaze Development Kit Board Configuration Mode Jumper Settings (Header J30 in Figure 4-2) Configuration Mode BPI Down Mode Pins M2:M1:M0 011 (see Chapter 11, “Intel StrataFlash Parallel NOR Flash PROM”) JTAG 101 FPGA Configuration Image Source StrataFlash parallel Flash PROM, starting at address 0x1FF_FFFF and decrementing through address space. The CPLD controls address lines A[24:20] during BPI configuration.
Programming the FPGA, CPLD, or Platform Flash PROM via USB R Programming the FPGA, CPLD, or Platform Flash PROM via USB As shown in Figure 4-1, page 24, the MicroBlaze Development Kit board includes embedded USB-based programming logic and an USB endpoint with a Type B connector. Via a USB cable connection with the host PC, the iMPACT programming software directly programs the FPGA, the Platform Flash PROM, or the on-board CPLD.
Chapter 4: FPGA Configuration Options R When the USB cable driver is successfully installed and the board is correctly connected to the PC, a green LED lights up, indicating a good connection. Programming via iMPACT After successfully compiling an FPGA design using the Xilinx development software, the design can be downloaded using the iMPACT programming software and the USB cable. To begin programming, connect the USB cable to the starter kit board and apply power to the board.
Programming the FPGA, CPLD, or Platform Flash PROM via USB R If the original FPGA configuration file used the default StartUp clock source, CCLK, iMPACT issues the warning message shown in Figure 4-7. This message can be safely ignored. When downloading via JTAG, the iMPACT software must change the StartUP clock source to use the TCK JTAG clock source.
Chapter 4: FPGA Configuration Options R UG257_09_061206 Figure 4-9: iMPACT Programming Succeeded, the FPGA’s DONE Pin is High Programming Platform Flash PROM via USB The on-board USB-JTAG circuitry also programs the two Xilinx XCF04S serial Platform Flash PROM. The steps provided in this section describe how to set up the PROM file and how to download it to the board to ultimately program the FPGA.
Programming the FPGA, CPLD, or Platform Flash PROM via USB R UG257_04_10_061206 Figure 4-10: Set Properties for Bitstream Generator Click Configuration Options as shown in Figure 4-11. Using the Configuration Rate drop list, choose 25 to increase the internal CCLK oscillator to approximately 25 MHz, the fastest frequency when using an XCF04S Platform Flash PROM. Click OK when finished.
Chapter 4: FPGA Configuration Options R To regenerate the programming file, double-click Generate Programming File, as shown in Figure 4-12. UG257_04_12_022706 Figure 4-12: Double-Click Generate Programming File Generating the PROM File After generating the program file, double-click Generate PROM, ACE, or JTAG File to launch the iMPACT software, as shown in Figure 4-13.
Programming the FPGA, CPLD, or Platform Flash PROM via USB R UG257_04_14_061206 Figure 4-14: Double-Click PROM File Formatter Choose Xilinx PROM as the target PROM type, as shown in Figure 4-15. Select from any of the PROM File Formats; the Intel Hex format (MCS) is popular. Enter the Location of the directory and the PROM File Name. Click Next > when finished.
Chapter 4: FPGA Configuration Options R The Spartan-3E Starter Kit board has an XCF04S Platform Flash PROM. Select xcf04s from the drop list, as shown in Figure 4-16. Click Add, then click Next >. UG257_4-16_061206 Figure 4-16: Choose the XCF04S Platform Flash PROM The PROM Formatter then echoes the settings, as shown in Figure 4-17. Click Finish. UG257_4-17_061206 Figure 4-17: 34 www.xilinx.
R Programming the FPGA, CPLD, or Platform Flash PROM via USB The PROM Formatter then prompts for the name(s) of the FPGA configuration bitstream file. As shown in Figure 4-18, click OK to start selecting files. Select an FPGA bitstream file (*.bit). Choose No after selecting the last FPGA file. Finally, click OK to continue.
Chapter 4: FPGA Configuration Options R UG257_4-19_061206 Figure 4-19: PROM Formatting Completed To generate the actual PROM file, click Operations Æ Generate File as shown in Figure 4-20. UG257_4-20_061206 Figure 4-20: Click Operations Æ Generate File to Create the Formatted PROM File The iMPACT software indicates that the PROM file was successfully created, as shown in Figure 4-21. 36 www.xilinx.com MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.
R Programming the FPGA, CPLD, or Platform Flash PROM via USB UG257 4 21 061206 Figure 4-21: PROM File Formatter Succeeded Programming the Platform Flash PROM To program the formatted PROM file into the Platform Flash PROM via the on-board USBJTAG circuitry, follow the steps outlined in this subsection. Place the iMPACT software in the JTAG Boundary Scan mode, either by choosing Boundary Scan in the iMPACT Modes pane, as shown in Figure 4-22, or by clicking on the Boundary Scan tab.
Chapter 4: FPGA Configuration Options R Assign the PROM file to the XCF04S Platform Flash PROM on the JTAG chain, as shown in Figure 4-23. Right-click the PROM icon, then click Assign New Configuration File. Select a previously generated PROM format file and click OK. UG257_4-23_060106 Figure 4-23: Assign the PROM File to the XCF04S Platform Flash PROM To start programming the PROM, right-click the PROM icon and then click Program..
R Programming the FPGA, CPLD, or Platform Flash PROM via USB Before programming, choose the programming options available in Figure 4-26. Checking the Erase Before Programming option erases the Platform Flash PROM completely before programming, ensuring that no previous data lingers. The Verify option checks that the PROM was correctly programmed and matches the downloaded configuration bitstream. Both these options are recommended even though they increase overall programming time.
Chapter 4: FPGA Configuration Options 40 www.xilinx.com R MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.
R Chapter 5 Character LCD Screen Overview The Spartan-3E MicroBlaze Development Kit board has been designed with a 16 pin female header connector. The Spartan-3E MicroBlaze Development board is shipped with a 2x16 LCD display attached, but any standard LCD display can be attached to this connector. The Spartan-3E MicroBlaze Development Kit board prominently features a 2-line by 16character liquid crystal display (LCD).
Chapter 5: Character LCD Screen R Once mastered, the LCD is a practical way to display a variety of information using standard ASCII and custom characters. However, these displays are not fast. Scrolling the display at half-second intervals tests the practical limit for clarity. Compared with the 50 MHz clock available on the board, the display is slow. A PicoBlaze processor efficiently controls display timing plus the actual content of the display.
Interaction with Intel StrataFlash R Interaction with Intel StrataFlash As shown in Figure 5-1, the four LCD data signals are also shared with StrataFlash data lines SF_D<11:8>. As shown in Table 5-2, the LCD/StrataFlash interaction depends on the application usage in the design. When the StrataFlash memory is disabled (SF_CE0 = High), then the FPGA application has full read/write access to the LCD.
Chapter 5: Character LCD Screen R LCD Controller The 2 x 16 character LCD has an internal Sitronix ST7066U graphics controller that is functionally equivalent with the following devices. x Samsung S6A0069X or KS0066U x Hitachi HD44780 x SMOS SED1278 Memory Map The controller has three internal memory regions, each with a specific purpose. The display must be initialized before accessing any of these memory regions.
LCD Controller R binary and the lower nibble equates to DB[3:0] = “0011” binary. As shown in Figure 5-4, the character ‘S’ appears on the screen. English/Roman characters are stored in CG ROM at their equivalent ASCII code address. Upper Data Nibble DB3 DB2 DB1 DB0 Lower Data Nibble DB7 DB6 DB5 DB4 Figure 5-4: UG257_05_04_061206 LCD Character Set The character ROM contains the ASCII English character set and Japanese kana characters.
Chapter 5: Character LCD Screen R The CG RAM address counter can either remain constant after read or write operations, or auto-increments or auto-decrements by one location, as defined by the I/D set by the Entry Mode Set command. Figure 5-5 provides an example, creating a special checkerboard character. The custom character is stored in the fourth CG RAM character location, which is displayed when a DD RAM location is 0x03.
LCD Controller R LCD Character Display Command Set (Continued) DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Lower Nibble LCD_RW Upper Nibble LCD_RS Table 5-3: Set CG RAM Address 0 0 0 1 A5 A4 A3 A2 A1 A0 Set DD RAM Address 0 0 1 A6 A5 A4 A3 A2 A1 A0 Read Busy Flag and Address 0 1 BF A6 A5 A4 A3 A2 A1 A0 Write Data to CG RAM or DD RAM 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Read Data from CG RAM or DD RAM 1 1 D7 D6 D5 D4 D3 D2 D1 D0 Function Disabled If the LCD_
Chapter 5: Character LCD Screen R This bit either auto-increments or auto-decrements the DD RAM and CG RAM address counter by one location after each Write Data to CG RAM or DD RAM or Read Data from CG RAM or DD RAM command. The cursor or blink position moves accordingly. Bit DB0: (S) Shift 0 Shifting disabled 1 During a DD RAM write operation, shift the entire display value in the direction controlled by Bit DB1 (I/D). Appears as though the cursor position remains constant and the display moves.
LCD Controller R Table 5-4: Shift Patterns According to S/C and R/L Bits DB3 DB2 (S/C) (R/L) Operation 0 0 Shift the cursor position to the left. The address counter is decremented by one. 0 1 Shift the cursor position to the right. The address counter is incremented by one. 1 0 Shift the entire display to the left. The cursor follows the display shift. The address counter is unchanged. 1 1 Shift the entire display to the right. The cursor follows the display shift.
Chapter 5: Character LCD Screen R After the write operation, the address is automatically incremented or decremented by 1 according to the Entry Mode Set command. The entry mode also determines display shift. Execution Time: 40 Ps Read Data from CG RAM or DD RAM Read data from DD RAM if the command follows a previous Set DD RAM Address command, or read data from CG RAM if the command follows a previous Set CG RAM Address command.
Operation R The data values on SF_D<11:8>, and the register select (LCD_RS) and the read/write (LCD_RW) control signals must be set up and stable at least 40 ns before the enable LCD_E goes High. The enable signal must remain High for 230 ns or longer—the equivalent of 12 or more clock cycles at 50 MHz. In many applications, the LCD_RW signal can be tied Low permanently because the FPGA generally has no reason to read information from the display.
Chapter 5: Character LCD Screen x R Finally, issue a Clear Display command. Allow at least 1.64 ms (82,000 clock cycles) after issuing this command. Writing Data to the Display To write data to the display, specify the start address, followed by one or more data values. Before writing any data, issue a Set DD RAM Address command to specify the initial 7-bit address in the DD RAM. See Figure 5-3 for DD RAM locations. Write data to the display using a Write Data to CG RAM or DD RAM command.
R Chapter 6 VGA Display Port The MicroBlaze Development Kit board includes a VGA display port via a J15 connector. Connect this port directly to most PC monitors or flat-panel LCDs using a standard monitor cable. As shown in Figure 6-1, the VGA connector is the left-most connector along the top of the board. Pin 5 DB15 VGA Connector Pin 1 (front view) in 10 DB15 VGA Connector Pin 6 n 15 Pin 11 DB15 Connector Red 1 270W (H14) VGA_RED 6 11 2 Green 270W Blue 270W Horizontal Sync 82.
Chapter 6: VGA Display Port R the VGA_RED, VGA_GREEN, and VGA_BLUE signals High or Low to generate the eight colors shown in Table 6-1. 3-Bit Display Color Codes Table 6-1: VGA_RED VGA_GREEN VGA_BLUE Resulting Color 0 0 0 Black 0 0 1 Blue 0 1 0 Green 0 1 1 Cyan 1 0 0 Red 1 0 1 Magenta 1 1 0 Yellow 1 1 1 White VGA signal timing is specified, published, copyrighted, and sold by the Video Electronics Standards Association (VESA).
Signal Timing for a 60 Hz, 640x480 VGA Display R pixel 0,0 pixel 0,639 640 pixels are displayed each time the beam traverses the screen VGA Display pixel 479,0 pixel 479,639 Current through the horizontal deflection coil Retrace: No information is displayed during this time Stable current ramp: Information is displayed during this time Total horizontal time Horizontal display time time "front porch" retrace time "front porch" HS Horizontal sync signal sets the retrace frequency "back porch" UG2
Chapter 6: VGA Display Port R display is redrawn. The minimum refresh frequency is a function of the display’s phosphor and electron beam intensity, with practical refresh frequencies in the 60 Hz to 120 Hz range. The number of horizontal lines displayed at a given refresh frequency defines the horizontal retrace frequency. VGA Signal Timing The signal timings in Table 6-2 are derived for a 640-pixel by 480-row display using a 25 MHz pixel clock and 60 Hz ± 1 refresh.
UCF Location Constraints R UCF Location Constraints Figure 6-4 provides the UCF constraints for the VGA display port, including the I/O pin assignment, the I/O standard used, the output slew rate, and the output drive current.
Chapter 6: VGA Display Port 58 www.xilinx.com R MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.
R Chapter 7 RS-232 Serial Ports Overview As shown in Figure 7-1, the MicroBlaze Development Kit board has two RS-232 serial ports: a female DB9 DCE connector and a male DTE connector. The DCE-style port connects directly to the serial port connector available on most personal computers and workstations via a standard straight-through serial cable. Null modem, gender changers, or crossover cables are not required.
Chapter 7: RS-232 Serial Ports R Pin 5 Pin 1 Std 9-Pin Serial cable RS-232 Peripheral TALK/DATA TALK RS CS TR RD TD CD Pin 6 Pin 9 To DTE DB9 Serial Port Connector (front view) Null Modem Serial cable Std 9-Pin Serial cable OR To DTE To DCE DTE DCE DCE Female DB9 5 J9 4 9 3 8 DTE Male DB9 2 7 1 5 6 4 9 3 8 2 7 1 6 J10 GND GND (R7) (M14) RS232_DTE_TXD RS232_DTE_RXD RS232_DCE_TXD RS232_DCE_RXD RS-232 Voltage Translator (IC2) (U8) (M13) Spartan-3E FPGA UG257_07_01_060506
UCF Location Constraints R UCF Location Constraints Figure 7-2 and Figure 7-3 provide the UCF constraints for the DTE and DCE RS-232 ports, respectively, including the I/O pin assignment and the I/O standard used.
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R Chapter 8 PS/2 Mouse/Keyboard Port The MicroBlaze Development Kit board includes a PS/2 mouse/keyboard port and the standard 6-pin mini-DIN connector, labeled J14 on the board. Figure 8-1 shows the PS/2 connector, and Table 8-1 shows the signals on the connector. Only pins 1 and 5 of the connector attach to the FPGA.
Chapter 8: PS/2 Mouse/Keyboard Port R Both a PC mouse and keyboard use the two-wire PS/2 serial bus to communicate with a host device, the Spartan-3E FPGA in this case. The PS/2 bus includes both clock and data. Both a mouse and keyboard drive the bus with identical signal timings and both use 11-bit words that include a start, stop and odd parity bit. However, the data packets are organized differently for a mouse and keyboard.
Keyboard R Some keys, called extended keys, send an “E0” ahead of the scan code and furthermore, they might send more than one scan code. When an extended key is released, an “E0 F0” key-up code is sent, followed by the scan code.
Chapter 8: PS/2 Mouse/Keyboard Port R The keyboard sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by eight bits of scan code (LSB first), followed by an odd parity bit and terminated with a ‘1’ stop bit. When the keyboard sends data, it generates 11 clock transitions at around 20 to 30 kHz, and data is valid on the falling edge of the clock as shown in Figure 8-2.
Voltage Supply R the X or Y values exceed their maximum value, an overflow condition. A ‘1’ indicates when an overflow occurs. If the mouse moves continuously, the 33-bit transmissions repeat every 50 ms or so. The L and R fields in the status byte indicate Left and Right button presses. A ‘1’ indicates that the associated mouse button is being pressed. Voltage Supply The PS/2 port on the MicroBlaze Development Kit board is powered by 5V.
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R Chapter 9 Digital to Analog Converter (DAC) The MicroBlaze Development Kit board includes an SPI-compatible, four-channel, serial Digital-to-Analog Converter (DAC). The DAC device is a Linear Technology LTC2624 quad DAC with 12-bit unsigned resolution. The four outputs from the DAC appear on the J5 header, which uses the Digilent 6-pin Peripheral Module format. The DAC and the header are located immediately above the Ethernet RJ-45 connector, as shown in Figure 9-1.
Chapter 9: Digital to Analog Converter (DAC) R LTC 2624 DAC Header J5 REF A 3.3V REF B REF C 2.5V REF D SPI_MOSI (T4) DAC_CS (N8) SPI_SCK (U16) (P8) VOUTA A DAC B VOUTB B DAC C VOUTC C DAC D VOUTD D 12 12 12 12 Spartan-3E FPGA (N10) DAC A DAC_CLR SDI CS/LD SCK SDO SPI Control Interface VCC (3.3V) CLR SPI_MISO Figure 9-2: GND UG257_09_02_060606 Digital-to-Analog Connection Schematics Interface Signals Table 9-1 lists the interface signals between the FPGA and the DAC.
SPI Communication R Although the StrataFlash PROM is a parallel device, its least-significant data bit is shared with the SPI_MISO signal. Table 9-2: Disabled Devices on the SPI Bus Signal Disabled Device Disable Value SPI_SS_B SPI serial Flash 1 AMP_CS Programmable pre-amplifier 1 AD_CONV Analog-to-Digital Converter (ADC) 0 SF_CE0 StrataFlash Parallel Flash PROM 1 FPGA_INIT_B Platform Flash PROM 1 SPI Communication Details Figure 9-3 shows a detailed example of the SPI bus timing.
Chapter 9: Digital to Analog Converter (DAC) R master. The response from the DAC can be ignored although it is a useful to confirm correct communication.
UCF Location Constraints R DAC Outputs C and D Equation 9-3 provides the output voltage equation for DAC outputs A and B. The reference voltage associated with DAC outputs A and B is 2.5V r 5%. D > 11:0 @ V OUTC = --------------------- u 2.5V r 5% 4096 Equation 9-3 UCF Location Constraints Figure 9-5 provides the UCF constraints for the DAC interface, including the I/O pin assignment and the I/O standard used.
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R Chapter 10 Analog Capture Circuit The MicroBlaze Development Kit board includes a two-channel analog capture circuit, consisting of aprogrammable scaling pre-amplifier and an analog-to-digital converter (ADC), as shown in Figure 10-1. Analog inputs are supplied on the J7 header.
Chapter 10: Analog Capture Circuit R Header J7 REFAB (3.3V) LTC 6912-1 AMP REFCD (2.5V) LTC 1407A-1 ADC –A VINA + + –B VINB + GND – A/D Channel 0 + A/D 14 – Channel 1 VCC (3.3V) 14 REF = 1.65V Spartan-3E FPGA SPI_MOSI DIN DOUT (N10) (T4) (E18) (N7) AMP_CS 0 1 2 3 0 1 2 3 B GAIN CS/LD A GAIN (U16) SPI_SCK SCK SPI Control Interface SCK SHDN CONV (P7) (P11) AMP_SHDN 0 ... 13 0 ...
Programmable Pre-Amplifier R The reference design files provide more information on converting the voltage applied on VINA or VINB to a digital representation (see “Related Resources,” page 81). Programmable Pre-Amplifier The LTC6912-1 provides two independent inverting amplifiers with programmable gain. The purpose of the amplifier is to scale the incoming voltage on VINA or VINB so that it maximizes the conversion range of the DAC, namely 1.65 r 1.25V.
Chapter 10: Analog Capture Circuit Table 10-2: R Programmable Gain Settings for Pre-Amplifier (Continued) A3 A2 A1 A0 Input Voltage Range B3 B2 B1 B0 Minimum Maximum -50 0 1 1 0 1.625 1.675 -100 0 1 1 1 1.6375 1.6625 Gain SPI Control Interface Figure 10-3 highlights the SPI-based communications interface with the amplifier. The gain for each amplifier is sent as an 8-bit command word, consisting of two 4-bit fields. The most-significant bit, B3, is sent first.
Analog to Digital Converter (ADC) R UCF Location Constraints Figure 10-5 provides the User Constraint File (UCF) constraints for the amplifier interface, including the I/O pin assignment and I/O standard used.
Chapter 10: Analog Capture Circuit R SPI_MISO Spartan-3E FPGA Master Slave: LTC1407A-1 A/D Converter 60 61 62 63 64 65 66 67 68 69 610 611 612 613 AD_CONV SPI_SCK Z 60 61 62 63 64 65 66 67 68 69 610 611 612 613 Z Channel 1 Z Channel 0 Converted data is presented with a latency of one sample. The sampled analog value is converted to digital data 32 SPI_SCK cycles after asserting AD_CONV. The converted values is then presented after the next AD_CONV pulse.
Disable Other Devices on the SPI Bus to Avoid Contention R NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ; NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ; UG257_10_08_061406 Figure 10-8: UCF Location Constraints for the ADC Interface Disable Other Devices on the SPI Bus to Avoid Contention The SPI bus signals are shared by other devices on the board.
Chapter 10: Analog Capture Circuit 82 www.xilinx.com R MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.
R Chapter 11 Intel StrataFlash Parallel NOR Flash PROM As shown in Figure 11-1, the MicroBlaze Development Kit boards includes a 128 Mbit (16 Mbyte) Intel StrataFlash parallel NOR Flash PROM. As indicated, some of the StrataFlash connections are shared with other components on the board.
Chapter 11: Intel StrataFlash Parallel NOR Flash PROM R x Stores MicroBlaze processor code in the StrataFlash device and shadows the code into the DDR memory before executing the code. x Stores non-volatile data from the FPGA. StrataFlash Connections Table 11-1 shows the connections between the FPGA and the StrataFlash device. Although the XC1600E FPGA only requires just slightly under 6 Mbits per configuration image, the FPGA-to-StrataFlash interface on the board support up to a 256 Mbit StrataFlash.
StrataFlash Connections R Table 11-1: Address Category FPGA-to-StrataFlash Connections StrataFlash Signal Name FPGA Pin Number SF_A24 A11 SF_A23 N11 SF_A22 V12 SF_A21 V13 SF_A20 T12 SF_A19 V15 SF_A18 U15 SF_A17 T16 SF_A16 U18 SF_A15 T17 SF_A14 R18 SF_A13 T18 SF_A12 L16 SF_A11 L15 SF_A10 K13 SF_A9 K12 SF_A8 K15 SF_A7 K14 SF_A6 J17 SF_A5 J16 SF_A4 J15 SF_A3 J14 SF_A2 J12 SF_A1 J13 SF_A0 H17 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide U
Chapter 11: Intel StrataFlash Parallel NOR Flash PROM Table 11-1: Control Data Category R FPGA-to-StrataFlash Connections StrataFlash Signal Name FPGA Pin Number SF_D15 T8 SF_D14 R8 SF_D13 P6 SF_D12 M16 SF_D11 M15 SF_D10 P17 SF_D9 R16 SF_D8 R15 SF_D7 N9 SF_D6 M9 SF_D5 R9 SF_D4 U9 SF_D3 V9 SF_D2 R10 SF_D1 P10 SPI_MISO N10 Bit 0 of data byte and 16-bit halfword. Connects to FPGA pin D0/DIN to support the BPI configuration.
Shared Connections R Shared Connections Besides the connections to the FPGA, the StrataFlash memory shares some connections to other components. Character LCD The LCD supports an 8-bit or a 4-bit data interface. The eight display data connections are also shared with the SF_D<15:8> signals on the StrataFlash PROM. As shown in Table 11-2, the FPGA controls access to the StrataFlash PROM or the character LCD using the SF_CE0 and LCD_RW signals.
Chapter 11: Intel StrataFlash Parallel NOR Flash PROM R UCF Location Constraints Address Figure 11-2 provides the UCF constraints for the StrataFlash address pins, including the I/O pin assignment and the I/O standard used.
Setting the FPGA Mode Select Pins R Control Figure 11-4 provides the UCF constraints for the StrataFlash control pins, including the I/O pin assignment and the I/O standard used.
Chapter 11: Intel StrataFlash Parallel NOR Flash PROM 90 www.xilinx.com R MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.
R Chapter 12 SPI Serial Flash The MicroBlaze Development Kit board includes a STMicroelectronics M25P16 16 Mbit SPI serial Flash, useful in a variety of applications. The SPI Flash provides an alternative means to configure the FPGA—a new feature of Spartan-3E FPGAs as shown in Figure 12-1. The SPI Flash is also available to the FPGA after configuration for a variety of purposes, such as: x Simple non-volatile data storage x Storage for identifier codes, serial numbers, IP addresses, etc.
Chapter 12: SPI Serial Flash R UCF Location Constraints Figure 12-2 provides the UCF constraints for the SPI serial Flash PROM, including the I/O pin assignment and the I/O standard used.
Configuring from SPI Flash R M0 M1 M2 J30 UG257_12_04_061506 Figure 12-4: Set Mode Pins for SPI Mode Creating an SPI Serial Flash PROM File The following steps describe how to format an FPGA bitstream for an SPI Serial Flash PROM. Setting the Configuration Clock Rate The FPGA supports a 12 MHz configuration clock rate when connected to an M25P16 SPI serial Flash. Set the Properties for Generate Programming File so that the Configuration Rate is 12, as shown in Figure 12-5.
Chapter 12: SPI Serial Flash R Formatting an SPI Flash PROM File After generating the program file, double-click Generate PROM, ACE, or JTAG File to launch the iMPACT software, as shown in Figure 12-6. UG257_12_06_060806 Figure 12-6: Double-Click Generate PROM, ACE, or JTAG File After iMPACT starts, double-click PROM File Formatter, as shown in Figure 12-7. UG257_12_07_060806 Figure 12-7: Double-Click PROM File Formatter Choose 3rd Party SPI PROM as the target PROM type, as shown in Figure 12-8.
Configuring from SPI Flash R UG257_12_08_060806 Figure 12-8: Choose the PROM Target Type, the, Data Format, and File Location The Spartan-3E Starter Kit board has a 16 Mbit SPI serial Flash PROM. Select 16M from the drop list, as shown in Figure 12-9. Click Next >. UG257_12_09_060806 Figure 12-9: MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 Choose 16M 95 www.xilinx.
Chapter 12: SPI Serial Flash R The PROM Formatter then echoes the settings, as shown in Figure 12-10. Click Finish. UG257_12_10_060806 Figure 12-10: Click Finish after Entering PROM Formatter Settings The PROM Formatter then prompts for the name(s) of the FPGA configuration bitstream file. As shown in Figure 12-11, click OK to start selecting files. Select an FPGA bitstream file (*.bit). Choose No after selecting the last FPGA file. Finally, click OK to continue.
Configuring from SPI Flash R UG257_12-12_062606 Figure 12-12: PROM Formatting Completed To generate the actual PROM file, click Operations Æ Generate File as shown in Figure 12-13. UG257_12_13_060806 Figure 12-13: Click Operations Æ Generate File to Create the Formatted PROM File As shown in Figure 12-14, the iMPACT software indicates that the PROM file was successfully created. The PROM Formatter creates an output file based on the settings shown in Figure 12-8.
Chapter 12: SPI Serial Flash R UG257_12_14_060806 Figure 12-14: PROM File Formatter Succeeded Downloading the Design to SPI Flash There multiple methods to program the SPI Flash, as listed below. x Use the XSPI programming software provided with XAPP445. Download the SPI Flash via the parallel port using a JTAG parallel programming cable (not provided with the kit). x Use the PicoBlaze based SPI Flash programmer reference designs.
Configuring from SPI Flash R First, turn off the power on the Spartan-3E Starter Kit board. If the USB cable is attached to the board, disconnect it. Simultaneously connecting both the USB cable and the parallel cable to the PC confuses the iMPACT software. Connect one end of the JTAG parallel programming cable to the parallel printer port of the PC. Connect the JTAG end of the cable to Header J12, as shown in Figure 12-15(a).
Chapter 12: SPI Serial Flash PROG GND JP8 PROG GND PROG a) No Jumper: FPGA Operational (default) DEFAULT NO JUMPER JP8 DEFAULT NO JUMPER R PROG b) Jumper Installed: FPGA Held in Configuration State, I/Os in High Impedance UG257_12_16_061506 Figure 12-16: Installing the JP8 Jumper Holds the FPGA in Configuration State Re-apply power to the MicroBlaze Development Kit board.
Additional Design Details R After programming the SPI Flash, remove jumper JP8, as shown in Figure 12-16(a). If properly programmed, the FPGA then configures itself from the SPI Flash PROM and the DONE LED lights. The DONE LED is shown in Figure 12-3, page 92. Additional Design Details Figure 12-18 provides additional details of the SPI Flash interface used on the Spartan-3E Starter Kit board. In most applications, this interface is as simple as that shown in Figure 12-1, page 91.
Chapter 12: SPI Serial Flash R Table 12-3: Disable Other Devices on SPI Bus Signal Disabled Device Disable Value AD_CONV Analog-to-Digital Converter (ADC) 0 SF_CE0 StrataFlash Parallel Flash PROM 1 FPGA_INIT_B Platform Flash PROM 1 Other SPI Flash Control Signals The M25P16 SPI Flash has two additional control inputs. The active-Low write protect input (W) and the active-Low bus hold input (HLD) are unused and pulled High via an external pull-up resistor.
Additional Design Details R x Density migration between smaller- and larger-density SPI Flash PROMs. Not all SPI Flash densities are available in all packages. The SPI Flash migration strategy follows nicely with the pinout migration provided by Xilinx FPGAs. x Consistent configuration PROM layout when migrating between FPGA densities. The Spartan-3E FPGA’s FG320 package footprint supports the XC3S500E, the XC3S1200E, and the XC3S1600E FPGA devices without modification.
Chapter 12: SPI Serial Flash R Related Resources 104 www.xilinx.com x XAPP445: Configuring Spartan-3E Xilinx FPGAs with SPI Flash Memories x http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category= Application+Notes/FPGA+Features+and+Design/Configuration&show=xapp445.p df x XSPI SPI Flash Programming Utility x http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category= Application+Notes/FPGA+Features+and+Design/Configuration&show=xapp445.
R Chapter 13 DDR SDRAM The MicroBlaze Development Kit board includes a 512 Mbit (32M x 16) Micron Technology DDR SDRAM (MT46V32M16) with a 16-bit data interface, as shown in Figure 13-1. All DDR SDRAM interface pins connect to the FPGA’s I/O Bank 3 on the FPGA. I/O Bank 3 and the DDR SDRAM are both powered by 2.5V, generated by an LTC3412 regulator from the board’s 5V supply input. The 1.25V reference voltage, common to the FPGA and DDR SDRAM, is generated using a resistor voltage divider from the 2.
Chapter 13: DDR SDRAM R The differential clock pin SD_CK_P is fed back into FPGA pin B9 in I/O Bank 0 to have best access to one of the FPGA’s Digital Clock Managers (DCMs). This path is required when using the MicroBlaze OPB DDR controller. The MicroBlaze OPB DDR SDRAM controller IP core documentation is also available from within the EDK 8.1i development software (see “Related Resources,” page 109). DDR SDRAM Connections Table 13-1 shows the connections between the FPGA and the DDR SDRAM.
DDR SDRAM Connections R Table 13-1: Control Data Category FPGA-to-DDR SDRAM Connections (Continued) DDR SDRAM Signal Name FPGA Pin Number SD_DQ15 H5 SD_DQ14 H6 SD_DQ13 G5 SD_DQ12 G6 SD_DQ11 F2 SD_DQ10 F1 SD_DQ9 E1 SD_DQ8 E2 SD_DQ7 M6 SD_DQ6 M5 SD_DQ5 M4 SD_DQ4 M3 SD_DQ3 L4 SD_DQ2 L3 SD_DQ1 L1 SD_DQ0 L2 SD_BA1 K6 SD_BA0 K5 SD_RAS C1 SD_CAS C2 SD_WE D1 SD_CK_N J4 SD_CK_P J5 SD_CKE K3 Active-High clock enable input SD_CS K4 Active-Low chip select input
Chapter 13: DDR SDRAM R UCF Location Constraints Address Figure 13-2 provides the User Constraint File (UCF) constraints for the DDR SDRAM address pins, including the I/O pin assignment and the I/O standard used.
Related Resources R Control Figure 13-4 provides the User Constraint File (UCF) constraints for the DDR SDRAM control pins, including the I/O pin assignment and the I/O standard used.
Chapter 13: DDR SDRAM 110 www.xilinx.com R MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.
R Chapter 14 10/100 Ethernet Physical Layer Interface The MicroBlaze Development Kit board includes a Standard Microsystems LAN83C185 10/100 Ethernet physical layer (PHY) interface and an RJ-45 connector, as shown in Figure 14-1. With an Ethernet Media Access Controller (MAC) implemented in the FPGA, the board can optionally connect to a standard Ethernet network. All timing is controlled from an on-board 25 MHz crystal oscillator.
Chapter 14: 10/100 Ethernet Physical Layer Interface R Ethernet PHY Connections The FPGA connects to the LAN83C185 Ethernet PHY using a standard Media Independent Interface (MII), as shown in Figure 14-2. A more detailed description of the interface signals, including the FPGA pin number, appears in Table 14-1.
MicroBlaze Ethernet IP Cores R Table 14-1: FPGA Connections to the LAN83C185 Ethernet PHY (Continued) Signal Name FPGA Pin Number E_RX_CLK V3 Receive Clock. 25 MHz in 100Base-TX mode, and 2.5 MHz in 10Base-T mode. E_CRS U13 Carrier Sense E_COL U6 MII Collision Detect. E_MDC P9 Management Clock. Serial management clock. E_MDIO U5 Management Data Input/Output. Function MicroBlaze Ethernet IP Cores The Ethernet PHY is primarily intended for use with MicroBlaze applications.
Chapter 14: 10/100 Ethernet Physical Layer Interface R The hardware evaluation versions of the Ethernet MAC cores operate for approximately eight hours in silicon before timing out. To order the full version of the core, visit the Xilinx website at: http://www.xilinx.com/ipcenter/processor_central/processor_ip/10-100emac/ 10-100emac_order_register.
R Chapter 15 Expansion Connectors The MicroBlaze Development Kit board provides a variety of expansion connectors for easy interface flexibility to other off-board components.
Chapter 15: Expansion Connectors R Spartan-3E FPGA (See Table) (See Table) (C3) (C15) (E10) (D10) (D9) Hirose 100-pin Expansion Connector (J3) FX2_IO<34:1> FX2_IP<38:35> FX2_IO<39> FX2_IP<40> FX2_CLKIN FX2_CLKOUT FX2_CLKIO (See Table) (See Table) (A.44) (A.45) (B.46) (A.47) (B.48) Bank 0 Supply (JP9) 2.5V 3.3V 5.
Hirose 100-pin FX2 Edge Connector (J3) R Table 15-1: Hirose 100-pin FX2 Connector Pinout and FPGA Connections (J3) Shared Header Connections A (top) B (bottom) VCCO_ 0 1 1 VCCO_ 0 2 2 TMS_B 3 3 TDO_XC2C JTSEL 4 4 TCK_B TDO_FX2 5 5 GND GND Signal Name FPGA Pin FX2 Connector LED J6 FPGA Pin Signal Name SHIELD GND GND FX2_IO1 B4 6 6 GND GND FX2_IO2 A4 7 7 GND GND FX2_IO3 D5 8 8 GND GND FX2_IO4 C5 9 9 GND GND FX2_IO5 A6 10 10 GND GND
Chapter 15: Expansion Connectors Table 15-1: R Hirose 100-pin FX2 Connector Pinout and FPGA Connections (J3) Shared Header Connections Signal Name FPGA Pin FX2_IO28 FX2 Connector A (top) B (bottom) FPGA Pin Signal Name B16 33 33 GND GND FX2_IO29 E13 34 34 GND GND FX2_IO30 C4 35 35 GND GND FX2_IO31 B11 36 36 GND GND FX2_IO32 A11 37 37 GND GND FX2_IO33 A8 LED7 38 38 GND GND FX2_IO34 G9 LED6 39 39 GND GND FX2_IP35 A7 LED5 40 40 GND GND FX2_IP36 D13
Hirose 100-pin FX2 Edge Connector (J3) R Spartan-3E data sheet. Select pairs have optional landing pads for external termination resistors. These signals are not routed with matched differential impedance, as would be required for ultimate performance. However, all traces have similar lengths to minimize skew.
Chapter 15: Expansion Connectors Table 15-2: Differential Pair 15 16 R Differential I/O Pairs (Continued) Signal Name FX2_IP35 D12 IP_L07N_0 Input FX2_IP36 C12 IP_L07P_0 Input FX2_IP37 A15 IP_L02N_0 Input FX2_IP38 B15 IP_L02P_0 Input E10 IO_L11N_0/ GCLK5 I/O D10 IO_L11P_0/ GCLK4 I/O FX2_ 17 FPGA Pins FPGA Pin Name Direction DIFF_TERM CLKIN FX2_ CLKOUT External Resistor Designator R208 R209 Yes R210 Yes Using Differential Inputs LVDS and RSDS differential inputs require input t
Hirose 100-pin FX2 Edge Connector (J3) R UG257_15_04_060806 Figure 15-4: Location of Termination Resistor Pads on Top Side of Board UG257_15_05_060806 Figure 15-5: Location of Termination Resistor Pads on Bottom Side of Board Using Differential Outputs Differential input signals do not require any special voltage. LVDS and RSDS differential outputs signals, on the other hand, require a 2.5V supply on I/O Bank 0. The board provides the option to power I/O Bank 0 with either 3.3V or 2.5V.
Chapter 15: Expansion Connectors R UCF Location Constraints Figure 15-7 provides the UCF constraints for the FX2 connector, including the I/O pin assignment and the I/O standard used, assuming that all connections use single-ended I/O standards. These header connections are shared with the 6-pin accessory headers, as shown in Figure 15-11, page 124.
Six-Pin Accessory Headers R Six-Pin Accessory Headers The 6-pin accessory headers provide easy I/O interface expansion using the various Digilent Peripheral Modules (see “Related Resources,” page 126). The location of the 6-pin headers is provided in Figure 15-1, page 115. Header J1 The J1 header, shown in Figure 15-8, is the top-most 6-pin connector along the right edge of the board. It uses a female 6-pin 90° socket. Four FPGA pins connect to the J1 header, J1<4:1>. The board supplies 3.
Chapter 15: Expansion Connectors R Header J4 The J4 header, shown in Figure 15-10, is located immediately to the left of the J1 header. It uses a 6-pin header consisting of 0.1-inch centered stake pins. Four FPGA pins connect to the J4 header, J4<4:1>. Four FPGA pins connect to the J4<4:1> header. The board supplies 3.3V to the accessory board mounted in the J4 socket on the bottom pin. J4 Spartan-3E FPGA (R14) J4<0> (T14) J4<1> (R13) J4<2> (P13) J4<3> GND 3.
Connectorless Debugging Port Landing Pads (J6) R Connectorless Debugging Port Landing Pads (J6) Landing pads for a connectorless debugging port are provided as header J6, shown in Figure 15-1, page 115. There is no physical connector on the board. Instead a connectorless probe, such as those available from Agilent, provides an interface to a logic analyzer. This debugging port is intended primarily for the Xilinx ChipScope Pro software with the Agilent’s FPGA Dynamic Probe.
Chapter 15: Expansion Connectors R Related Resources x Hirose connectors http://www.hirose-connectors.com/ x FX2 Series Connector Data Sheet http://www.hirose.co.jp/cataloge_hp/e57220088.pdf x Digilent, Inc. Peripheral Modules http://www.digilentinc.com/Products/Catalog.cfm?Nav1=Products&Nav2=Peripheral&Cat=Peripheral x Xilinx ChipScope Pro Tool http://www.xilinx.com/ise/optional_prod/cspro.htm x Agilent B4655A FPGA Dynamic Probe for Logic Analyzer http://www.home.agilent.
R Chapter 16 XC2C64A CoolRunner-II CPLD The MicroBlaze Development Kit board includes a Xilinx XC2C64A CoolRunner-II CPLD. The CPLD is user programmable and available for customer applications. Portions of the CPLD are reserved to coordinate behavior between the various FPGA configuration memories, namely the Xilinx Platform Flash PROM and the Intel StrataFlash PROM. Consequently, the CPLD must provide the following functions in addition to the user application.
Chapter 16: XC2C64A CoolRunner-II CPLD R 3.
UCF Location Constraints R FPGA Connections to CPLD Figure 16-2 provides the UCF constraints for the FPGA connections to the CPLD , including the I/O pin assignment and the I/O standard used.
Chapter 16: XC2C64A CoolRunner-II CPLD R Related Resources x CoolRunner-II CPLD Family Data Sheet http://direct.xilinx.com/bvdocs/publications/ds090.pdf x XC2C64A CoolRunner-II CPLD Data Sheet http://direct.xilinx.com/bvdocs/publications/ds311.pdf x Default XC2C64A CPLD Design for Spartan-3E Starter Kit Board http://www.xilinx.com/s3estarter 130 www.xilinx.com MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.
R Chapter 17 DS2432 1-Wire SHA-1 EEPROM The MicroBlaze Development Kit board includes a Maxim DS2432 serial EEPROM with an integrated SHA-1 engine. As shown in Figure 17-1, the DS2432 EEPROM uses the Maxim 1-Wire interface, which uses a single wire for power and serial communication. The DS2432 EEPROM offers one of many possible means to copy and protect the FPGA configuration bitstream, thereby making cloning difficult.
Chapter 17: DS2432 1-Wire SHA-1 EEPROM 132 www.xilinx.com R MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.
R Appendix A Schematics This appendix provides the following circuit board schematics: x “FX2 Expansion Header, 6-pin Headers, and Connectorless Probe Header” x “RS-232 Ports, VGA Port, and PS/2 Port” x “Ethernet PHY, Magnetics, and RJ-11 Connector” x “Voltage Regulators” x “FPGA Configurations Settings, Platform Flash PROM, SPI Serial Flash, JTAG Connections” x “FPGA I/O Banks 0 and 1, Oscillators” x “FPGA I/O Banks 2 and 3” x “Power Supply Decoupling” x “XC2C64A CoolRunner-II CPLD” x “
Appendix A: Schematics R FX2 Expansion Header, 6-pin Headers, and Connectorless Probe Header Headers J1, J2, and J4 are six-pin connectors compatible with the Digilent Accessory board format. Headers J3A and J3B are the connections to the FX2 expansion connector located along the right edge of the board. Header J5 provides the four analog outputs from the Digital-to-Analog Converter (DAC). Header J6 is the landing pad for an Agilent or Tektronix connectorless probe.
R FX2 Expansion Header, 6-pin Headers, and Connectorless Probe Header UG257_A01_060606 Figure 18-1: Schematic Sheet 1 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 135 www.xilinx.
Appendix A: Schematics R RS-232 Ports, VGA Port, and PS/2 Port IC2 is the Maxim LVTTL to RS-232 level converter. One of the serial channels connects to a female DB9 DCE connector (J9) and the other connects to a male DB9 DTE connector (J10). See Chapter 7, “RS-232 Serial Ports,” for additional information. Connector J14 is a PS/2-style mouse/keyboard connector, powered from 5 volts. See Chapter 8, “PS/2 Mouse/Keyboard Port,” for additional information.
RS-232 Ports, VGA Port, and PS/2 Port R UG257_A02_060606 Figure 18-2: Schematic Sheet 2 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 137 www.xilinx.
Appendix A: Schematics R Ethernet PHY, Magnetics, and RJ-11 Connector IC6 is an SMSC 10/100 Ethernet PHY, with its associated 25 MHz oscillator. The PHY requires an Ethernet MAC implemented within the FPGA. J19 is the RJ-11 Ethernet connector associated with the 10/100 Ethernet PHY. See Chapter 14, “10/100 Ethernet Physical Layer Interface,” for additional information. 138 www.xilinx.com MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.
Ethernet PHY, Magnetics, and RJ-11 Connector R UG257_A03_060606 Figure 18-3: Schematic Sheet 4 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 139 www.xilinx.
Appendix A: Schematics R Voltage Regulators IC7 is a Texas Instruments TPS75003 triple-output regulator. The regulator provides 1.2V to the FPGA’s VCCINT supply input, 2.5V to the FPGA’s VCCAUX supply input, and 3.3V to other components on the board and to the FPGA’s VCCO supply inputs on I/O Banks 0, 1, and 2. Jumpers JP6 and JP7 provide a means to measure current across the FPGA’s VCCAUX and VCCINT supplies respectively. IC8 is a Linear Technology LT3412 regulator, providing 2.
Voltage Regulators R UG257_A04_060606 Figure 18-4: Schematic Sheet 5 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 141 www.xilinx.
Appendix A: Schematics R FPGA Configurations Settings, Platform Flash PROM, SPI Serial Flash, JTAG Connections IC10MISC represents the various FPGA configuration connections. IC11 is a 4 Mbit XCF04S Platform Flash PROM. Landing pads for a second XCF04S PROM is shown as IC13, although the second PROM is not mounted on the XC3S500E version of the board. Resistor R100 jumpers over the JTAG chain, bypassing the second XCF04S PROM. Jumper header J30 selects the FPGA’s configuration mode.
R FPGA Configurations Settings, Platform Flash PROM, SPI Serial Flash, JTAG Connections UG257_A05_060606 Figure 18-5: Schematic Sheet 6 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 143 www.xilinx.
Appendix A: Schematics R FPGA I/O Banks 0 and 1, Oscillators IC10B0 represents the connections to I/O Bank 0 on the FPGA. The VCCO input to Bank 0 is 3.3V by default, but can be set to 2.5V using jumper JP9. IC10B1 represents the connections to I/O Bank 1 on the FPGA. IC17 is the 50 MHz clock oscillator. Chapter 3, “Clock Sources,” for additional information. IC16 is an 8-pin DIP socket to insert an alternate clock oscillator with a different frequency. 144 www.xilinx.
FPGA I/O Banks 0 and 1, Oscillators R UG257_A06_060606 Figure 18-6: Schematic Sheet 7 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 145 www.xilinx.
Appendix A: Schematics R FPGA I/O Banks 2 and 3 IC10B2 represents the connections to I/O Bank 2 on the FPGA. Some of the I/O Bank 2 connections are used for FPGA configuration and are listed as IC10MISC. IC10B3 represents the connections to I/O Bank 3 on the FPGA. Bank 3 is dedicated to the DDR SDRAM interface and is consequently powered by 2.5V. See Chapter 13, “DDR SDRAM,” for additional information. 146 www.xilinx.com MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.
FPGA I/O Banks 2 and 3 R UG257_A07_060606 Figure 18-7: Schematic Sheet 8 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 147 www.xilinx.
Appendix A: Schematics R Power Supply Decoupling IC10PWR represents the various voltage supply inputs to the FPGA and shows the power decoupling network. Jumper JP9 defines the voltage applied to VCCO on I/O Bank 0. The default setting is 3.3V. See “Voltage Control,” page 20 and “Voltage Supplies to the Connector,” page 116 for additional details. 148 www.xilinx.com MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.
Power Supply Decoupling R UG257_A08_060606 Figure 18-8: Schematic Sheet 9 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 149 www.xilinx.
Appendix A: Schematics R XC2C64A CoolRunner-II CPLD IC18 is a Xilinx XC2C64A CoolRunner-II CPLD. The CPLD primarily provides additional flexibility when configuring the FPGA from parallel NOR Flash and during MultiBoot configurations. When the CPLD is loaded with the appropriate design, JP10 enables a watchdog timer in the CPLD used during fail-safe MultiBoot configurations. See Chapter 16, “XC2C64A CoolRunner-II CPLD,” for more information. 150 www.xilinx.
XC2C64A CoolRunner-II CPLD R UG257_A09_060606 Figure 18-9: Schematic Sheet 10 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 151 www.xilinx.
Appendix A: Schematics R Linear Technology ADC and DAC IC19 is a Linear Technology LTC1407A-1 two-channel ADC. IC20 is a Linear Technology LTC6912 programmable pre-amplifier (AMP) to condition the analog inputs to the ADC. See Chapter 10, “Analog Capture Circuit,” for additional information. IC21 is a Linear Technology LTC2624 four-channel DAC. See Chapter 9, “Digital to Analog Converter (DAC),” for additional information. 152 www.xilinx.
Linear Technology ADC and DAC R UG257_A10_060606 Figure 18-10: Schematic Sheet 11 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 153 www.xilinx.
Appendix A: Schematics R Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM IC22 is a 128 Mbit (16 Mbyte) Intel StrataFlash parallel NOR Flash PROM. See Chapter 11, “Intel StrataFlash Parallel NOR Flash PROM,” for additional information. IC23 is a 512 Mbit (64 Mbyte) Micron DDR SDRAM. See Chapter 13, “DDR SDRAM,” for additional information. 154 www.xilinx.com MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.
R Intel StrataFlash Parallel NOR Flash Memory and Micron DDR SDRAM UG257_A11_060606 Figure 18-11: Schematic Sheet 12 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 155 www.xilinx.
Appendix A: Schematics R Buttons, Switches, Rotary Encoder, and Character LCD SW0, SW1, SW2, and SW3 are slide switches. Push-button switches W, E, S, and N are located around the ROT1 push-button switch/rotary encoder. LD0 through LD7 are discrete LEDs. See Chapter 2, “Switches, Buttons, and Knob,” for additional information. DISP1 is a 2x16 character LCD screen. See Chapter 5, “Character LCD Screen,” for additional information. 156 www.xilinx.
Buttons, Switches, Rotary Encoder, and Character LCD R UG257_A12_060606 Figure 18-12: Schematic Sheet 13 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 157 www.xilinx.
Appendix A: Schematics R DDR SDRAM Series Termination and FX2 Connector Differential Termination Resistors R160 through R201 represent the series termination resistors for the DDR SDRAM. See Chapter 13, “DDR SDRAM,” for additional information. Resistors R202 through R210 are not loaded on the board. These landing pads provide optional connections for 100: differential termination resistors. See “Using Differential Inputs,” page 120 for additional information. 158 www.xilinx.
R DDR SDRAM Series Termination and FX2 Connector Differential Termination UG257_A13_060606 Figure 18-13: Schematic Sheet 14 MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.1) December 5, 2007 159 www.xilinx.
Appendix A: Schematics 160 www.xilinx.com R MicroBlaze Development Kit Spartan-3E 1600 Edition User Guide UG257 (v1.
R Appendix B Example User Constraints File (UCF) ################################################################ ### SPARTAN-3E MicroBlaze Development KIT BOARD CONSTRAINTS FILE ################################################################ # ==== FPGA Configuration Mode, INIT_B Pins (FPGA) ==== NET "FPGA_M0" LOC = "M10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "FPGA_M1" LOC = "V11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "FPGA_M2" LOC = "T10" | IOSTANDARD = LVCMOS33 | SLE
Appendix Appendix B: Example User Constraints File (UCF) R # These are shared connections with the FX connector NET "LED<0>" LOC = "D4" | IOSTANDARD = SSTL2_I ; NET "LED<1>" LOC = "C3" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; # FX2-IO39 NET "LED<2>" LOC = "D6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; # FX2-IO38 NET "LED<3>" LOC = "E6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; # FX2-IO37 NET "LED<4>" LOC = "D13" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ; # FX2-IO36 NET "LED<5>"
R NET "E_RXD<4>" LOC = "U14" | IOSTANDARD = LVCMOS33 ; NET "E_TX_CLK" LOC = "T7" | IOSTANDARD = LVCMOS33 ; NET "E_TX_EN" LOC = "P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "E_TXD<0>" LOC = "R11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "E_TXD<1>" LOC = "T15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "E_TXD<2>" LOC = "R5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "E_TXD<3>" LOC = "T5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; NET "E_TXD<4
Appendix Appendix B: Example User Constraints File (UCF) R CONFIG PROHIBIT = R4; # ==== Intel StrataFlash Parallel NOR Flash (SF) ==== NET "SF_A<0>" LOC = "H17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<1>" LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<2>" LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<3>" LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ; NET "SF_A<4>" LOC = "J15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 |
R NET "VGA_VSYNC" LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ; # # ==== FX2 Connector (FX2) ==== NET "FX2_CLKIN" LOC = "E10" | IOSTANDARD = LVCMOS33 ; NET "FX2_CLKIO" LOC = "D9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_CLKOUT" LOC = "D10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<1>" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<2>" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; NET "FX2_IO<3>" LOC = "D5"
Appendix Appendix B: Example User Constraints File (UCF) R # ==== 6-pin header J4 ==== # These are independent of the FX2 connector #NET "J4<0>" LOC = "R14" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; #NET "J4<1>" LOC = "T14" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; #NET "J4<2>" LOC = "R13" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; #NET "J4<3>" LOC = "P13" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ; # # ==== J15 Input Only Connector ==== NET "INPUT_IO<1>" LOC = "A12" | PULLDOWN |
