LogiCORE™ IP Endpoint Block Plus v1.
R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx.
Table of Contents Preface: About This Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Typographical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Online Document . . . . . . . . . . .
Dual Core Example Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Dual Core Directory Structure and File Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . /example_design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . example_design/dual_core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . /simulation . . . . . . . . .
R Preface About This Guide The Endpoint Block Plus for PCI Express® Getting Started Guide provides information about generating an Endpoint Block Plus for PCI Express (PCIe®) core, customizing and simulating the core using the provided example design, and running the design files through implementation using the Xilinx tools. Contents This guide contains the following chapters: • Preface, “About this Guide,” introduces the organization and purpose of this guide and the conventions used in this document.
R Preface: About This Guide Convention Meaning or Use Example References to other manuals See the User Guide for details. Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected. User-defined variable for directory names. Dark Shading Items that are not supported or reserved Unsupported feature Square brackets An optional entry or parameter.
R Chapter 1 Introduction The Endpoint Block Plus for PCI Express is a high-bandwidth, scalable, and reliable serial interconnect building block for use with Virtex™-5 FPGA devices. This core supports Verilog® and VHDL. The example design described in this guide is provided in Verilog and VHDL. This chapter introduces the core and provides related information, including system requirements, recommended design experience, additional resources, technical support, and submitting feedback to Xilinx.
R Chapter 1: Introduction performance, pipelined FPGA designs using Xilinx implementation software and User Constraints Files (UCF) is recommended. Additional Core Resources For detailed information and updates about the core, see the following documents, available from the Block Plus for PCIe product page unless otherwise noted.
R Feedback Document For comments or suggestions about this document, please submit a WebCase from www.xilinx.com/support. Be sure to include the following information: • Document title • Document number • Page number(s) to which your comments refer • Explanation of your comments Endpoint Block Plus v1.8 for PCI Express UG343 June 27, 2008 www.xilinx.
R Chapter 1: Introduction 10 www.xilinx.com Endpoint Block Plus v1.
R Chapter 2 Licensing the Core This chapter provided licensing options for the Endpoint Block Plus for PCI Express core, which you must do before using the core in your designs. The core is provided under the terms of the Xilinx LogiCORE Site License Agreement, which conforms to the terms of the SignOnce IP License standard defined by the Common License Consortium.
R Chapter 2: Licensing the Core Obtaining Your License Simulation Only Evaluation License The Simulation Only Evaluation license is provided with the CORE Generator system and requires no license file. Obtaining a Full License To obtain a Full license, you must register for access to the lounge, a secured area of the Block Plus for PCIe product page. • From the product page, click Register to register and request access to the lounge. Access to the lounge is automatic and granted immediately.
R Chapter 3 Quickstart Example Design This chapter provides an overview of the Endpoint Block Plus for PCI Express example design (both single and dual core) and instructions for generating the core. It also includes information about simulating and implementing the example design using the provided demonstration test bench. Overview The example simulation design consists of two discrete parts: • The Downstream Port Model, a test bench that generates, consumes, and checks PCI Express bus traffic.
R Chapter 3: Quickstart Example Design Output Logs Downstream Port Model TPI for PCI Express usrapp_com Test Program usrapp_tx usrapp_rx dsport PCI Express Fabric Endpoint Core for PCI Express PIO Design Endpoint DUT for PCI Express Figure 3-1: Simulation Example Design Block Diagram 14 www.xilinx.com Endpoint Block Plus v1.
R Overview Implementation Design Overview The implementation design consists of a simple PIO example that can accept read and write transactions and respond to requests, as illustrated in Figure 3-2. Source code for the example is provided with the core. For more information about the PIO example design, see Appendix A, “Programmed Input Output Example Design,” in the LogiCORE IP Endpoint Block Plus for PCI Express User Guide (UG341).
R Chapter 3: Quickstart Example Design Generating the Core To generate a core using the default values in the CORE Generator Graphical User Interface (GUI), do the following: 1. Start the CORE Generator. For help starting and using the CORE Generator, see the Xilinx CORE Generator Guide, available from the ISE documentation web page. 2. Choose File > New Project. Figure 3-3: New Project Dialog Box 3. Enter a project name and location, then click OK. is used in this example.
R Generating the Core 4. Set the project options: From the Part tab, select the following options: • Family: Virtex5 • Device: xc5vlx50t • Package: ff1136 • Speed Grade: -1 Note: If an unsupported silicon device is selected, the core is dimmed (unavailable) in the list of cores. From the Generation tab, select the following parameters, and then click OK. • Design Entry. Select either VHDL or Verilog. • Vendor. Select Synplicity® or ISE (for XST). 5.
R Chapter 3: Quickstart Example Design Simulating the Example Design The example design provides a quick way to simulate and observe the behavior of the core. The simulation environment provided with the Block Plus core performs simple memory access tests on the PIO example design. Transactions are generated by the Downstream Port Model and responded to by the PIO example design. • PCI Express Transaction Layer Packets (TLPs) are generated by the test bench transmit user application (pci_exp_usrapp_tx).
R Implementing the Example Design 2. Run the script that corresponds to your simulation tool using one of the following: • VCS: simulate_vcs.sh • Cadence IUS: simulate_ncsim.sh • ModelSim: vsim -do simulate_mti.do Implementing the Example Design After generating the core, the netlists and the example design can be processed using the Xilinx implementation tools. The generated output files include scripts to assist you in running the Xilinx software.
R Chapter 3: Quickstart Example Design • routed.sdf Timing model Standard Delay File. • mapped.mrp Xilinx map report. • routed.par Xilinx place and route report. • routed.twr Xilinx timing analysis report. The script file starts from an EDIF/NGC file and results in a bitstream file. It is possible to use the Xilinx ISE GUI to implement the example design. However, the GUI flow is not presented in this document.
R Directory Structure and File Contents The project directory contains all the CORE Generator project files. Table 3-1: Project Directory Name Description .ngc Top-level netlist. .v[hd] Verilog or VHDL simulation model. .xco CORE Generator project-specific option file; can be used as an input to the CORE Generator. _flist.txt List of files delivered with core. .
R Chapter 3: Quickstart Example Design /example_design The example design directory contains the example design files provided with the core. Table 3-4: Example Design Directory Name Description //example_design pci_exp_8_lane_64b_ep.v pci_exp_4_lane_64b_ep.v pci_exp_1_lane_64b_ep.v Verilog top-level port list, applicable to the 8-lane, 4-lane, and 1-lane endpoint design, respectively. .ucf Example design UCF.
R Directory Structure and File Contents implement/results The results directory is created by the implement script, after which the implement script results are placed in the results directory. Table 3-6: Results Directory Name Description //implement/results Implement script result files. Back to Top /simulation The simulation directory contains the simulation source files provided with the core.
R Chapter 3: Quickstart Example Design simulation/dsport The dsport directory contains the data stream simulation scripts provided with the core. Table 3-8: dsport Directory Name Description //simulation/dsport dsport_cfg.v[hd] pci_exp_expect_tasks.v pci_exp_1_lane_64b_dsport.v[hd] pci_exp_4_lane_64b_dsport.v[hd] pci_exp_usrapp_cfg.v[hd] pci_exp_usrapp_com.v pci_exp_usrapp_rx.v[hd] pci_exp_usrapp_tx.v[hd] xilinx_pci_exp_downstream_port.v[hd] xilinx_pci_exp_dsport.
R Dual Core Example Design simulation/tests The tests directory contains test definitions for the example test bench. Table 3-10: Tests Directory Name Description //simulation/tests pio_tests.v sample_tests1.v tests.v[hd] Test definitions for example test bench. Back to Top Dual Core Example Design The dual core example design can be used as a starting point for designs with multiple Virtex-5 FPGA PCI Express blocks.
R Chapter 3: Quickstart Example Design xilinx_dual_pci_exp_ep xilinx_pci_exp_primary_ep xilinx_pci_exp_secondary_ep pci_exp_64b_app pci_exp_64b_app PIO PIO Endpoint Core Endpoint Core Figure 3-6: Dual Core Design Block Diagram Dual Core Directory Structure and File Contents When generating the Block Plus core with the Virtex-5 FX70T-FF1136 (XC5VFX70T-FF1136) FPGA, the PIO example design source files and scripts are generated using the directory structure specified in the “Directory Structure and
R Dual Core Example Design /example_design The example design directory includes the dual core example design ucf, which varies based on the device selected. Table 3-11: Example Design Directory Name Description xilinx_dual_*.ucf Dual core example design ucf. Varies by lane-width, part, and package selected. Back to Top example_design/dual_core The dual core directory contains the top-level and wrapper files for the dual core example design.
R Chapter 3: Quickstart Example Design simulation/functional The functional directory contains the dual core example design simulation scripts. Table 3-14: Functional Directory Name Description simulate_dual_mti.do ModelSim simulation script. simulate_dual_ncsim.sh Cadence IUS simulation script. simulate_dual_vcs.sh VCS simulation script. board_dual_rtl_x0*.f List of files for RTL simulations. board_dual_rtl_x0*_ncv.f List of files for RTL simulations.
R Appendix Additional Design Considerations Package Constraints This appendix describes design considerations specific to the Endpoint Block Plus for PCIe core. Table A-1 lists the smallest supported device and interface combinations for the Block Plus core. Table A-1: Supported Device and Interface Combinations Smallest Supported Device/Part Number Data Bus Width/Speed Wrapper File XC5VLX20T FF323-1 Width: 64-bit Port Speed: 62.5 MHz xilinx_pci_exp_1_lane_ep.
R 30 Appendix Appendix: Additional Design Considerations www.xilinx.com Endpoint Block Plus v1.
