Inc. Network Card User Manual

ManualsBrandsXilinx ManualsNetwork CardLOGICORE UG144

-- DISCONTINUED PRODUCT --

LogiCORE™ IP

1-Gigabit Ethernet

MAC v8.5

User Guide

UG144 April 24, 2009

Summary of content (138 pages)

PAGE 1
-- DISCONTINUED PRODUCT -- LogiCORE™ IP 1-Gigabit Ethernet MAC v8.
PAGE 2
-- DISCONTINUED PRODUCT -- R Xilinx is providing this product documentation, hereinafter “Information,” to you “AS IS” with no warranty of any kind, express or implied. Xilinx makes no representation that the Information, or any particular implementation thereof, is free from any claims of infringement. You are responsible for obtaining any rights you may require for any implementation based on the Information. All specifications are subject to change without notice.
PAGE 3
-- DISCONTINUED PRODUCT -- Revision History The following table shows the revision history for this document. Date Version Revision 09/30/04 1.0 Initial Xilinx release. 04/28/05 2.0 Updated to 1-Gigabit Ethernet MAC version 6.0, Xilinx tools v7.1i SP1. 01/18/06 3.0 Updated to 1-Gigabit Ethernet MAC version 7.0, Xilinx tools v8.1i. 07/13/06 4.0 Updated to 1-Gigabit Ethernet MAC version 8.0, Xilinx tools v8.2i. 09/21/06 4.1 Updated to 1-Gigabit Ethernet MAC version 8.
PAGE 4
-- DISCONTINUED PRODUCT -- www.xilinx.com 1-Gigabit Ethernet MAC v8.
PAGE 5
-- DISCONTINUED PRODUCT -- Table of Contents Schedule of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Schedule of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Preface: About This Guide Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Conventions . . . . .
PAGE 6
-- DISCONTINUED PRODUCT -R Chapter 4: Designing with the Core General Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Design Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Know the Degree of Difficulty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keep it Registered . . . . . . . . . . . . . . . . . . . . . . .
PAGE 7
-- DISCONTINUED PRODUCT -- Connecting the MDIO to an Internally Integrated PHY . . . . . . . . . . . . . . . . . . . . . . . . 76 Connecting the MDIO to an External PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Chapter 8: Configuration and Status Using the Optional Management Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Host Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 8
-- DISCONTINUED PRODUCT -R Chapter 12: Implementing Your Design Pre-implementation Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Using the Simulation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 XST—VHDL . . . . . . . . . . . . . . . . . . . . . .
PAGE 9
-- DISCONTINUED PRODUCT -- Schedule of Figures Chapter 1: Introduction Chapter 2: Core Architecture Figure 2-1: Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 2-2: Component Pinout for MAC with Optional Management Interface . . . . . . 23 Figure 2-3: Component Pinout for MAC without Optional Management Interface and with Optional Address Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 10
-- DISCONTINUED PRODUCT -R Chapter 7: Using the Physical Side Interface Figure 7-1: External GMII Transmitter Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figure 7-2: External GMII Receiver Logic for Spartan-3, Spartan-3E, and Spartan-3A Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 7-3: External GMII Receiver Logic for Virtex-5 Devices . . . . . . . . . . . . . . . . . . . . .
PAGE 11
-- DISCONTINUED PRODUCT -R Chapter 11: Interfacing to Other Cores Figure 11-1: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS with TBI 114 Figure 11-2: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and PMA using a RocketIO Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Figure 11-3: 1-Gigabit Ethernet MAC Extended to Include 1000BASE-X PCS and PMA using a RocketIO transceiver. . . . . . . . . . . . . . . . . . . . . . . .
PAGE 12
-- DISCONTINUED PRODUCT -R 12 www.xilinx.com 1-Gigabit Ethernet MAC v8.
PAGE 13
-- DISCONTINUED PRODUCT -- Schedule of Tables Chapter 1: Introduction Chapter 2: Core Architecture Table 2-1: Transmitter Client Interface Signal Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 2-2: Receive Client Interface Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 2-3: Flow Control Interface Signal Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 14
-- DISCONTINUED PRODUCT -R Table 8-8: Unicast Address Word 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 8-9: Unicast Address Word 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 8-10: Address Table Configuration Word 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 8-11: Address Table Configuration Word 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 15
-- DISCONTINUED PRODUCT -R Preface About This Guide The LogiCORE™ IP 1-Gigabit Ethernet MAC User Guide provides information about generating the core, customizing and simulating the core utilizing the provided example design, and running the design files through implementation using the Xilinx tools. Guide Contents This guide contains the following chapters: • Preface, “About this Guide” introduces the organization and purpose of the guide and the conventions used in this document.
PAGE 16
-- DISCONTINUED PRODUCT -R Preface: About This Guide Conventions This document uses the following conventions. An example illustrates each convention.
PAGE 17
-- DISCONTINUED PRODUCT -R Conventions Online Document The following linking conventions are used in this document: Convention Meaning or Use Blue text Cross-reference link to a location in the current document Blue, underlined text Hyperlink to a website (URL) Example See the section “Additional Resources” for details. See “Title Formats” in Chapter 1 for details. Go to www.xilinx.com for the latest speed files. List of Acronyms The following table describes acronyms used in this manual.
PAGE 18
-- DISCONTINUED PRODUCT -R Preface: About This Guide Acronym 18 Spelled Out NCD Native Circuit Description NGC Native Generic Circuit NGD Native Generic Database ns nanoseconds PCB Printed Circuit Board PCS Physical Coding Sublayer PHY physical-side interface PMA Physical Medium Attachment PMD Physical Medium Dependent RGMII Reduced Gigabit Media Independent Interface SGMII Serial Gigabit Media Independent Interface VHDL VHSIC Hardware Description Language (VHSIC an acronym for V
PAGE 19
-- DISCONTINUED PRODUCT -R Chapter 1 Introduction The 1-Gigabit Ethernet MAC (GEMAC) core is a fully verified solution that supports Verilog-HDL and VHDL. In addition, the example design provided with the core is provided in both Verilog and VHDL. This chapter introduces the GEMAC core and provides other related information, including recommended design experience, additional resources, technical support, and ways to submit feedback to Xilinx.
PAGE 20
-- DISCONTINUED PRODUCT -R Chapter 1: Introduction Specifications • IEEE 802.3 2005 • Reduced Gigabit Media Independent Interface (RGMII) version 2.0 Technical Support For technical support, see support.xilinx.com/. Questions are routed to a team of engineers with expertise using the GEMAC core. Xilinx will provide technical support for use of this product as described in the 1-Gigabit Ethernet MAC User Guide and the 1-Gigabit Ethernet MAC Getting Started Guide.
PAGE 21
-- DISCONTINUED PRODUCT -R Chapter 2 Core Architecture This chapter describes the GEMAC core architecture, including the major functional blocks and all interfaces. System Overview Figure 2-1 illustrates a block diagram of the GEMAC core with all the major functional blocks and interfaces. Descriptions of the functional blocks and interfaces are provided in the sections that follow.
PAGE 22
-- DISCONTINUED PRODUCT -R Chapter 2: Core Architecture Core Components Transmit Engine The Transmit Engine accepts Ethernet frame data from the Client Transmitter Interface, adds the preamble field to the start of the frame, adds padding bytes (if required) to ensure that the frame meets the minimum frame length requirements, and adds the frame check sequence (when configured to do so). The transmitter also ensures that the inter-frame spacing between successive frames is at least the minimum specified.
PAGE 23
-- DISCONTINUED PRODUCT -R Core Interfaces Core Interfaces GMAC Core with Optional Management Interface Figure 2-2 shows the pinout for the GEMAC core using the optional Management Interface. The interface is unchanged, regardless of whether the optional Address Filter is included.
PAGE 24
-- DISCONTINUED PRODUCT -R Chapter 2: Core Architecture GMAC Core Without Management Interface and With Address Filter Figure 2-3 shows the pinout for the GEMAC core when the optional Management Interface is omitted and the optional Address Filter is included in the core. The configuration_vector[67:0] input provides the method for configuration of the core, and mac_unicast_address[47:0] input provides the method of setting the unicast address used by the Address Filter.
PAGE 25
-- DISCONTINUED PRODUCT -R Core Interfaces GEMAC Core Without Management Interface and Without Address Filter Figure 2-4 shows the pinout for the GEMAC core when the optional Management Interface is omitted and the optional Address Filter is omitted. The configuration_vector[67:0] input provides the method for configuration of the core.
PAGE 26
-- DISCONTINUED PRODUCT -R Chapter 2: Core Architecture All ports of the core are internal connections in FPGA fabric. An HDL example design is delivered with the core that will add IBUFs, OBUFs, and IOB flip-flops to the external signals of the Gigabit Media Independent Interface (GMII) or Reduced Gigabit Media Independent Interface (RGMII). All clock management logic is placed in this example design, which allows for more flexibility in implementation (for example, in designs using multiple cores).
PAGE 27
-- DISCONTINUED PRODUCT -R Core Interfaces Receiver Interface Table 2-2 describes the client-side receiver signals of the GEMAC core. These signals are used by to transfer data to the client. See “Receiving Inbound Frames,” on page 39. Table 2-2: Receive Client Interface Signal Pins Signal Direction Clock Domain Description rx_data[7:0] Output gmii_rx_clk Frame data received is supplied on this port. rx_data_valid Output gmii_rx_clk Control signal for the rx_data port.
PAGE 28
-- DISCONTINUED PRODUCT -R Chapter 2: Core Architecture Management Interface (Optional) Table 2-4 describes the optional signals used by the client to access the management features of the GEMAC core. See “Using the Optional Management Interface,” on page 77. Table 2-4: Optional Management Interface Signal Pinout Direction Clock Domain host_clk Input n/a host_opcode[1:0] Input host_clk Defines operation to be performed over MDIO interface.
PAGE 29
-- DISCONTINUED PRODUCT -R Core Interfaces Configuration Vector (Optional) Table 2-6 describes the alternative to the optional Management Interface signals. The Configuration Vector uses direct inputs to the core to replace the functionality of the MAC configuration bits. See “Access without the Management Interface,” on page 90.
PAGE 30
-- DISCONTINUED PRODUCT -R Chapter 2: Core Architecture MDIO Interface Table 2-9 describes the MDIO Interface signals. See “Using the MDIO interface,” on page 76. Table 2-9: MDIO Interface Signal Pinout Direction Clock Domain Output host_clk Management Clock: programmable frequency derived from host_clk. Input host_clk Input data signal for communication with PHY configuration and status. Tie high if unused.
PAGE 31
-- DISCONTINUED PRODUCT -R Chapter 3 Generating the Core The GEMAC core is generated through the Xilinx CORE Generator™ using a graphical user interface (GUI). This chapter describes the GUI options used to generate and customize the core. Graphical User Interface Figure 3-1 shows the main GEMAC core user GUI screen.
PAGE 32
-- DISCONTINUED PRODUCT -R Chapter 3: Generating the Core Component Name The component name is used as the base name of the output files generated for the core. Names must begin with a letter and must be composed from the following characters: a through z, 0 through 9 and “_”. Management Interface Select this option to include the optional Management Interface (see “Using the Optional Management Interface,” on page 77).
PAGE 33
-- DISCONTINUED PRODUCT -R Output Generation Table 3-1: XCO File Values and Default Values Parameter XCO File Values Default GUI Setting component_name ASCII text starting with a letter and based upon the following character set: a..z, 0..
PAGE 34
-- DISCONTINUED PRODUCT -R 34 Chapter 3: Generating the Core www.xilinx.com 1-Gigabit Ethernet MAC v8.
PAGE 35
-- DISCONTINUED PRODUCT -R Chapter 4 Designing with the Core This chapter provides general guidelines for creating designs using the GEMAC core. To work with the example design included with the GEMAC core, see the 1-Gigabit Ethernet MAC Getting Started Guide. General Design Guidelines This section describes the steps required to turn a GEMAC core into a fully functioning design integrated with user-application logic. Not all implementations require all the design steps described in this chapter.
PAGE 36
-- DISCONTINUED PRODUCT -R Chapter 4: Designing with the Core Statistics Vectors Interface _example_design _locallink _block Clock/ Reset Circuitry 1-Gigabit Ethernet MAC Core Address Swap Module LocalLink Interface 10 Mbps, 100 Mbps Client 1 Gbps Ethernet FIFO Interface Tx Client FIFO Physical Interface GMII/ RGMII Interface Logic, IOBs and Clock Management Rx Client FIFO Management Interface Figure 4-1: 1-Gigabit Ethernet MAC Core Example Design
PAGE 37
-- DISCONTINUED PRODUCT -R General Design Guidelines Implementing the 1-Gigabit Ethernet MAC in Your Application The example design can be studied as an example of how to do the following: • Instantiate the core from HDL. • Source and use the client-side interface ports of the core from application logic. • Connect the physical-side interface of the core (GMII or RGMII) to device IOBs to create an external interface. • Derive the clock management logic.
PAGE 38
-- DISCONTINUED PRODUCT -R Chapter 4: Designing with the Core See also Appendix C, “Calculating DCM Phase-Shifting” to meet Spartan-3, Spartan-3E and Spartan-3A device setup and hold requirements for external GMII.
PAGE 39
-- DISCONTINUED PRODUCT -R Chapter 5 Using the Client Side Data Path This chapter provides general guidelines for creating designs using the GEMAC core, including a detailed description of each client-side data flow interface of the core. Definitions of the abbreviations used throughout the remainder of this chapter are defined in Table 5-1.
PAGE 40
-- DISCONTINUED PRODUCT -R Chapter 5: Using the Client Side Data Path gmii_rx_clk rx_data[7:0] DA SA L/T DATA rx_data_valid rx_good_frame rx_bad_frame Figure 5-1: Normal Frame Reception Frame parameters (destination address, source address, length/type and optionally FCS) are supplied on the data bus according to the timing diagram.
PAGE 41
-- DISCONTINUED PRODUCT -R Receiving Inbound Frames Frame Reception with Errors Figure 5-2 illustrates an unsuccessful frame reception (for example, a fragment frame or a frame with an incorrect FCS). In this case, the rx_bad_frame signal is asserted to the client at the end of the frame. It is then the responsibility of the client to drop the data already transferred for this frame. The following conditions cause the assertion of rx_bad_frame: • FCS errors occur.
PAGE 42
-- DISCONTINUED PRODUCT -R Chapter 5: Using the Client Side Data Path Client-Supplied FCS Passing If the GEMAC core is configured to pass the FCS field to the client (see “Configuration Registers,” on page 78), this is handled as shown in Figure 5-3. In this case, any padding inserted into the frame to meet Ethernet minimum frame length specifications will be left intact and passed to the client.
PAGE 43
-- DISCONTINUED PRODUCT -R Receiving Inbound Frames Maximum Permitted Frame Length The maximum legal length of a frame specified in IEEE 802.3-2005 is 1518 bytes for nonVLAN tagged frames. VLAN tagged frames may be extended to 1522 bytes. When jumbo frame handling is disabled and the core receives a frame which exceeds the maximum legal length, rx_bad_frame is asserted. When jumbo frame handling is enabled, frames which are longer than the legal maximum are received in the same way as shorter frames.
PAGE 44
-- DISCONTINUED PRODUCT -R Chapter 5: Using the Client Side Data Path Address Filter If the optional Address Filter is included in the core, the MAC is able to reject frames that do not contain a known address in their destination address field. If a frame is rejected, the rx_data_valid signal is not asserted for the duration of the frame. In addition, neither rx_good_frame or rx_bad_frame are asserted at the end of the frame.
PAGE 45
-- DISCONTINUED PRODUCT -R Receiving Inbound Frames Table 5-2: Bit Definition for the Receiver Statistics Vector rx_statistics_vector bit(s) Name Description 27 Address Match If the optional Address Filter is included in the core, this bit is asserted if the address of the incoming frame matches one of the stored or pre-set addresses in the Address Filter. If the Address Filter is omitted from the core, or is configured in promiscuous mode, this line is held high. 26 Reserved Always at logic 0.
PAGE 46
-- DISCONTINUED PRODUCT -R Chapter 5: Using the Client Side Data Path Table 5-2: Bit Definition for the Receiver Statistics Vector rx_statistics_vector bit(s) Name Description 20 Out of Bounds Asserted if the previous frame exceeded the specified IEEE802.3-2005 maximum legal length (see “Maximum Permitted Frame Length”). This is only valid if jumbo frames are disabled. 19 Control Frame Asserted if the previous frame contained the special control frame identifier in the length/type field.
PAGE 47
-- DISCONTINUED PRODUCT -R Transmitting Outbound Frames Transmitting Outbound Frames Ethernet frames to be transmitted are presented to the client logic on the Transmitter subset of the Client-Side Interface. For port definition, see “Transmitter Interface,” on page 26. Normal Frame Transmission Figure 5-6 illustrates the timing of a normal outbound frame transfer. When the client wishes to transmit a frame, it places the first column of data onto the tx_data port and asserts a ‘1’ onto tx_data_valid.
PAGE 48
-- DISCONTINUED PRODUCT -R Chapter 5: Using the Client Side Data Path Client-Supplied FCS Passing The transmission timing depicted in Figure 5-7 shows the GEMAC core configured to have the FCS field passed in by the client. In this case, it is the responsibility of the client to ensure that the frame meets the Ethernet minimum frame length requirements as the GEMAC core will not perform any padding of the payload. See “Configuration Registers,” on page 78.
PAGE 49
-- DISCONTINUED PRODUCT -R Transmitting Outbound Frames VLAN Tagged Frames Figure 5-9 illustrates transmission of a VLAN tagged frame (if enabled). The handshaking signals across the interface do not change; however, the VLAN type tag 81-00 must be supplied by the client to signify that the frame is VLAN tagged. The client also supplies the two bytes of Tag Control Information, V1 and V2, at the appropriate times in the data stream.
PAGE 50
-- DISCONTINUED PRODUCT -R Chapter 5: Using the Client Side Data Path gtx_clk tx_data[7:0] DA SA DA tx_data_valid tx_ack tx_ifg_delay 0x0D Next IFG ADJUST VALUE IFG ADJUST VALUE 13 Idles inserted between the end of frame and the preamble field of the following frame Figure 5-10: Inter-Frame Gap Adjustment Transmitter Statistics Vector The statistics for the transmitted frame are contained within the tx_statistic_vector.
PAGE 51
-- DISCONTINUED PRODUCT -R Transmitting Outbound Frames Table 5-4: Bit Definition for the Transmitter Statistics Vector tx_statistics_vector bit(s) Name Description 31 Pause Frame Asserted if the previous frame was a pause frame that the MAC itself initiated in response to a pause_req assertion. 30 Byte Valid Asserted if a MAC frame byte (DA to FCS inclusive) is in the process of being transmitted. This is valid on every clock cycle.
PAGE 52
-- DISCONTINUED PRODUCT -R Chapter 5: Using the Client Side Data Path Table 5-5 provides conversion information against previous versions of the GEMAC. Table 5-5: Tx Statistics conversion to previous core GEMAC core versions Version 8.5 tx_statistics_vector bit(s) 52 Version 8.4 (and earlier) tx_statistics_vector bit(s) Notes 31 21 Bit 31 is equivalent to bit 21 of all previous core versions. 30 20 Bit 30 is equivalent to bit 20 of all previous core versions.
PAGE 53
-- DISCONTINUED PRODUCT -R Chapter 6 Using Flow Control This chapter describes the operation of the flow-control logic of the GEMAC core. The flow control block is designed to clause 31 of the IEEE 802.3-2005 standard. The MAC may be configured to transmit pause requests and to act on their reception; these modes of operation can be independently enabled or disabled. See “Flow Control Configuration,” on page 81.
PAGE 54
-- DISCONTINUED PRODUCT -R Chapter 6: Using Flow Control The user MAC on the left side has a reference clock slightly slower than the nominal 125 MHz. The link partner MAC on the right side has a reference clock slightly faster than the nominal 125 MHz. As a result, the user MAC receives data at a faster line rate than that at which it can transmit. The MAC on the left is shown performing a loopback implementation which results in the FIFO filling up over time.
PAGE 55
-- DISCONTINUED PRODUCT -R Overview of Flow Control Pause Control Frames Control frames are a unique type of Ethernet frame, defined in clause 31 of the IEEE 802.32005 standard. Control frames are differentiated from other frame types by a defined value placed in the length/type field (MAC Control Type code). Figure 6-2 illustrates the control frame format.
PAGE 56
-- DISCONTINUED PRODUCT -R Chapter 6: Using Flow Control Flow Control Operation of the GEMAC Transmitting a PAUSE Control Frame Core-initiated Pause Request If the GEMAC core is configured to support transmit flow control, the client can initiate a pause control frame by asserting pause_req (see “Flow Control Configuration,” on page 81). Figure 6-3 illustrates pause request timing.
PAGE 57
-- DISCONTINUED PRODUCT -R Flow Control Operation of the GEMAC Receiving a Pause Control Frame Core Initiated Response to a Pause Request An error free control frame is a received frame matching the format of Figure 6-2. It must pass all standard receiver frame checks (for example, FCS field checking).
PAGE 58
-- DISCONTINUED PRODUCT -R Chapter 6: Using Flow Control Flow Control Implementation Example This section provides a basic overview of a Flow Control implementation, using Figure 6-1 as a sample. To summarize the example, the user MAC on the left hand side of the figure cannot match the full line rate of the link partner MAC on the right hand side due to clock tolerances. Over time, the FIFO illustrated will fill and overflow.
PAGE 59
-- DISCONTINUED PRODUCT -R Flow Control Implementation Example Operation Figure 6-4 illustrates the FIFO occupancy over a period of time. Full FIFO occupancy A C 7/8 3/4 B 5/8 1/2 time Figure 6-4: Flow Control Implementation Triggered from FIFO Occupancy The following describes the sequence of flow control operation. 1. The average FIFO occupancy of the user system gradually increases over time due to the clock tolerances. At point A, the occupancy has reached the threshold of 7/8 occupancy.
PAGE 60
-- DISCONTINUED PRODUCT -R 60 Chapter 6: Using Flow Control www.xilinx.com 1-Gigabit Ethernet MAC v8.
PAGE 61
-- DISCONTINUED PRODUCT -R Chapter 7 Using the Physical Side Interface This chapter provides general guidelines for creating designs using the Physical Side Interface of the GEMAC core. The physical side interface implements GMII-style signaling and is typically attached to a physical layer device (PHY), either off-chip or internally integrated. See “Physical Side Interface” in Chapter 2.
PAGE 62
-- DISCONTINUED PRODUCT -R Chapter 7: Using the Physical Side Interface IOB LOGIC FDDRRSE IOB LOGIC IBUFG '0' BUFG D Q gtx_clk OBUF gtx_clk_bufg IPAD gmii_tx_clk OPAD '1' D Q D Q 1-Gigabit Ethernet MAC LogiCORE OBUF gtx_clk gmii_txd[0] gmii_txd_int[0] gmii_txd_reg[0] OPAD OBUF gmii_tx_en gmii_tx_en_int D Q D Q gmii_tx_en_reg Figure 7-1: 62 gmii_tx_er_int gmii_tx_en OPAD OBUF gmii_tx_er gmii_txd[0] gmii_tx_er_reg gmii_tx_er OPAD External GMII Transmitter Logic www.
PAGE 63
-- DISCONTINUED PRODUCT -R Implementing External GMII GMII Receiver Logic Spartan-3, Spartan-3E, Spartan-3A and Virtex-4 Devices A DCM must be used on the gmii_rx_clk clock path, as illustrated in Figure 7-2, to meet the input setup and hold requirements for GMII. This is performed by the example designs delivered with the core (all signal names and logic match Figure 7-2). This DCM circuitry may optionally be used in other families.
PAGE 64
-- DISCONTINUED PRODUCT -R Chapter 7: Using the Physical Side Interface DCM Reset circuitry A DCM reset module, not illustrated in Figure 7-2, is also present and is instantiated in the example design next to the DCM. Since this logic must be reliable whatever the reset/locked status of the DCM, the module requires a reliable reference clock. In the example design for GMII, the global transmitter clock is therefore used (gtx_clk_bufg from Figure 7-1).
PAGE 65
-- DISCONTINUED PRODUCT -R Implementing External GMII Virtex-5 Devices An IODELAY component may be used on the clock, data and control paths, as illustrated in Figure 7-3. These can be used to either shift the input clock gmii_rx_clk or the data and control signals to meet the setup and hold requirements of GMII and to allow for any bus skew across the data and control inputs. The IODELAY components are used in fixed delay mode, where the attribute IDELAY_VALUE determines the tap delay value.
PAGE 66
-- DISCONTINUED PRODUCT -R Chapter 7: Using the Physical Side Interface Implementing External RGMII The HDL example design delivered with the core implements an external RGMII when RGMII is selected from the CORE Generator GUI (see Chapter 3, “Generating the Core”). For more information about using the example design, see the 1-Gigabit Ethernet MAC Getting Started Guide.
PAGE 67
-- DISCONTINUED PRODUCT -R Implementing External RGMII Figure 7-4 shows that the output transmitter signals are registered on gtx_clk_bufg, in the FPGA fabric, including the encoded rgmii_tx_ctl_int signal, derived from the logical xor of gmii_tx_en_int and gmii_tx_er_int. The signals to be transmitted on the RGMII falling clock edge are then registered on the falling edge of this clock. This ensures that the data is presented to the Double Data Rate registers at the correct time.
PAGE 68
-- DISCONTINUED PRODUCT -R Chapter 7: Using the Physical Side Interface IOB LOGIC ODDR BUFGMUX IOB LOGIC DCM CLK90 rgmii_tx_clk_bufg IBUFG gtx_clk '1' D1 '0' D2 OBUF rgmii_txc Q OPAD CLKIN IPAD gtx_clk_bufg C CLK0 FB IOB LOGIC ODDR 1-Gigabit Ethernet MAC Core gmii_txd[0] gmii_txd[4] gtx_clk gmii_txd_int[0] OBUF D1 gmii_txd_int[4] rgmii_txd[0] D2 Q OPAD C IOB LOGIC ODDR gmii_tx_en gmii_tx_er gmii_tx_en_int gmii_tx_er_int OBUF D1 D2 rgmii_tx_ctl Q OPAD C Figure 7-5: Exte
PAGE 69
-- DISCONTINUED PRODUCT -R Implementing External RGMII Virtex-5 Devices The same logic that is used in Figure 7-5 can also be used without modification for Virtex-5 devices. However, an alternative solution has been adopted for the example design delivered with the core. Figure 7-6 shows using the physical transmitter interface of the core to create an external RGMII in a Virtex-5 device. The signal names and logic shown exactly match those delivered with the example design when the RGMII is selected.
PAGE 70
-- DISCONTINUED PRODUCT -R Chapter 7: Using the Physical Side Interface The logic required to forward the transmitter clock is also shown. It has matching logic to the data and control signals to provide a known relationship between the signals. An IODELAY component is used to phase-shift the rgmii_txc clock signal by 90 degrees with respect to gtx_clk_bufg.
PAGE 71
-- DISCONTINUED PRODUCT -R Implementing External RGMII IOB LOGIC BUFG IBUFG DCM CLK0 CLKIN 1-Gigabit Ethernet MAC Core rgmii_rxc IPAD FB gmii_rx_clk_bufg gmii_rx_clk IOB LOGIC rgmii_rxd_reg[0] rgmii_rxd_ddr[0] gmii_rxd[0] IBUF gmii_rxd_reg[0] Q D Q D Q D rgmii_rxd[0] IPAD rgmii_rxd_reg[4] rgmii_rxd_ddr[4] Q gmii_rxd[4] D Q D Q D gmii_rxd_reg[4] rgmii_rx_dv_reg rgmii_rx_dv_ddr gmii_rx_dv gmii_rx_dv_reg Q D Q D Q D IBUF rgmii_rx_ctl IPAD rgmii_rx_ctl_reg rgmii_rx_ctl_ddr gmi
PAGE 72
-- DISCONTINUED PRODUCT -R Chapter 7: Using the Physical Side Interface Virtex-4 Devices Figure 7-8 shows using the physical receiver interface of the core to create an external RGMII in a Virtex-4 device. The signal names and logic exactly match those delivered with the example design when RGMII is selected. Figure 7-8 also shows that the input receiver signals are registered in the IOBs in IDDR components. These components convert the input double data rate signals into GMII specification signals.
PAGE 73
-- DISCONTINUED PRODUCT -R Implementing External RGMII • This can be achieved by connecting the reset_200ms signal to the reset_200ms_in signal at any level of example design HDL hierarchy.
PAGE 74
-- DISCONTINUED PRODUCT -R Chapter 7: Using the Physical Side Interface Virtex-5 Devices Figure 7-9 shows using the physical receiver interface of the core to create an external RGMII in a Virtex-5 device. The signal names and logic exactly match those delivered with the example design when RGMII is selected. Figure 7-9 also shows that the input receiver signals are registered in the IOBs in IDDR components. These components convert the input double data rate signals into GMII specification signals.
PAGE 75
-- DISCONTINUED PRODUCT -R Implementing External RGMII RGMII Inband Status Decoding Logic The inband status decoding logic is common to all device families. Figure 7-10 illustrates the decoding of RGMII inband status information. This information is received through the RGMII interface between frames. The signal names and logic shown exactly match those delivered with the example design when the RGMII is selected.
PAGE 76
-- DISCONTINUED PRODUCT -R Chapter 7: Using the Physical Side Interface Using the MDIO interface The MDIO interface is accessed through the optional management interface and is typically connected to the MDIO port of a physical-layer device to access its configuration and status registers (see “MDIO Interface,” on page 86). The MDIO format is defined in IEEE 802.3, clause 22.
PAGE 77
-- DISCONTINUED PRODUCT -R Chapter 8 Configuration and Status This chapter provides general guidelines for configuring and monitoring the GEMAC core, including a detailed description of the client-side management interface and registers present in the core. It also describes the alternative to the optional management interface which is the Configuration Vector.
PAGE 78
-- DISCONTINUED PRODUCT -R Chapter 8: Configuration and Status Configuration Registers After a power-up or system reset, the client may reconfigure the core parameters using their defaults. Configuration changes can be written at any time. Both the receiver and transmitter logic responds only to configuration changes during inter-frame gaps. The exceptions to this are the configurable resets that take effect immediately.
PAGE 79
-- DISCONTINUED PRODUCT -R Using the Optional Management Interface Receiver Configuration The register contents for the two receiver configuration words are shown in Table 8-3 and Table 8-4. Table 8-3: Receiver Configuration Word 0 Default Value Bit 31-0 All 0s Description Pause frame MAC Source Address[31:0]. This address is used by the MAC to match against the destination address of any incoming flow control frames.
PAGE 80
-- DISCONTINUED PRODUCT -R Chapter 8: Configuration and Status Table 8-4: Bit Receiver Configuration Word 1 (Continued) Default Value Description 29 0 In-band FCS Enable When this bit is ‘1,’ the MAC receiver will pass the FCS field up to the client. When at ‘0,’ the client will not be passed the FCS. In both cases, the FCS will be verified on the frame. 30 0 Jumbo Frame Enable When this bit is set to ‘1,’ the MAC receiver will accept frames over the specified IEEE 802.32005 maximum legal length.
PAGE 81
-- DISCONTINUED PRODUCT -R Using the Optional Management Interface Table 8-5: Transmitter Configuration Word (Continued) Bit Default Value 29 0 In-band FCS Enable When this bit is ‘1,’ the MAC transmitter will expect the FCS field to be passed in by the client. When this bit is ‘0,’ the MAC transmitter will append padding as required, compute the FCS and append it to the frame.
PAGE 82
-- DISCONTINUED PRODUCT -R Chapter 8: Configuration and Status MDIO Configuration The register contents for the Management Configuration Word are described in Table 8-7. Table 8-7: Bits 4-0 Management Configuration Word Default Value All 0s 5 Clock Divide[4:0] This value enters a logical equation which enables the mdc frequency to be set as a divided down ratio of the host_clk frequency.
PAGE 83
-- DISCONTINUED PRODUCT -R Using the Optional Management Interface The Address Filter can be programmed to respond to four separate additional addresses stored in an address table in the Address Filter. Table 8-10 and Table 8-11 describe how the contents of the address table are set. Table 8-10: Address Table Configuration Word 0 Default Value Bits 31–0 All 0s Description MAC Address[31:0].
PAGE 84
-- DISCONTINUED PRODUCT -R Chapter 8: Configuration and Status host_clk host_miim_sel host_opcode[1] host_addr[8:0] host_addr[9] host_wr_data[31:0] Figure 8-1: Configuration Register Write Timing Reading from the configuration register words is similar, but the upper host_opcode bit should be ‘1,’ as shown in Figure 8-2. In this case, the contents of the register appear on host_rd_data the host_clk edge after the register address is asserted onto host_addr.
PAGE 85
-- DISCONTINUED PRODUCT -R Using the Optional Management Interface Accessing the Address Table To write to a specific entry in the address table, you must first write the least significant 32bits of the address into the Address Table Configuration (Word 0) register. You then write the most significant 16 bits together with the location in the table (bits 17–16) to the Address Table Configuration (Word1) register with bit 23 (read not write) set to ‘0.’ This is shown in Figure 8-3.
PAGE 86
-- DISCONTINUED PRODUCT -R Chapter 8: Configuration and Status hostclk hostmiimsel hostopcode[1] 0x18C hostaddr[8:0] hostaddr[9] hostwrdata[23] LOCATION hostwrdata[17:16] 31 : 0 hostrddata[31:0] Figure 8-4: 47 : 32 Address Table Read Timing MDIO Interface Introduction to MDIO The MDIO interface for 1 Gbps operation (and slower speeds) is defined in IEEE 802.3 clause 22. This is a two wire interface consisting of a clock, mdc, and a shared serial data line, mdio.
PAGE 87
-- DISCONTINUED PRODUCT -R Using the Optional Management Interface MAC 1 MAC 2 mdio STA Figure 8-5: mdc MMD MMD MMD MMD MMD MMD Typical MDIO-managed System There are two different transaction types of MDIO for write and read. They are described in this section. Abbreviations Used The following abbreviations apply for the remainder of this chapter.
PAGE 88
-- DISCONTINUED PRODUCT -R Chapter 8: Configuration and Status Read Transaction Figure 8-7 shows a Read transaction; this is defined by OP=”10”. The addressed MMD (PHYAD) device returns the 16-bit word from the register at REGAD.
PAGE 89
-- DISCONTINUED PRODUCT -R Using the Optional Management Interface Figure 8-8 shows access to the MDIO interface through the Management Interface. host_clk host_miim_sel host_req host_opcode1:0] host_addr9:0] host_wr_data15:0] * host_rdy host_rd_data[15:0] * * If a read transaction is initiated, the host_rd_data bus is valid at the point indicated. If a write transaction is initiated, the host_wr_data bus must be valid at the indicated point. Simultaneous read and write is not permitted.
PAGE 90
-- DISCONTINUED PRODUCT -R Chapter 8: Configuration and Status Access without the Management Interface If the optional management interface is omitted from the core, all of the relevant configuration settings described in Table 8-3 through Table 8-6 are brought out of the core as signals. These signals are bundled into the configuration_vector[67:0] signal as described in Table 8-13.
PAGE 91
-- DISCONTINUED PRODUCT -R Access without the Management Interface Table 8-13: Bit(s) Configuration Vector Bit Definition (Continued) Configuration Register cross reference Clock Description 53 “Receiver Configuration Word 1” bit 31 n/a Receiver Reset. When this bit is ‘1,’ the receiver is held in reset. This signal is an input to the reset circuit for the receiver block.
PAGE 92
-- DISCONTINUED PRODUCT -R Chapter 8: Configuration and Status Table 8-13: Bit(s) 92 Configuration Vector Bit Definition (Continued) Configuration Register cross reference Clock Description 62 “Flow Control Configuration Word” bit 30 gtx_clk Receive Flow Control Enable. When this bit is ‘1,’ received flow control frames will inhibit the transmitter operation. When at ‘0,’ received flow frames are passed up to the client.
PAGE 93
-- DISCONTINUED PRODUCT -R Chapter 9 Constraining the Core This chapter defines the GEMAC core constraint requirements. An example UCF that implements the constraints defined in this chapter is provided with the HDL example design for the core. See the 1-Gigabit Ethernet MAC Getting Started Guide for more information about the CORE Generator™ output files and detailed information about the HDL example design.
PAGE 94
-- DISCONTINUED PRODUCT -R Chapter 9: Constraining the Core PERIOD Constraints for Clock Nets gtx_clk The clock provided to gtx_clk must be constrained for a clock frequency of 125 MHz.
PAGE 95
-- DISCONTINUED PRODUCT -R Required Constraints The UCF syntax which follows targets the MDIO logic flip-flops and groups them together. Reduced clock period constraints are then applied.
PAGE 96
-- DISCONTINUED PRODUCT -R Chapter 9: Constraining the Core Timespecs for Reset Logic within the Core Internally, the core is divided into clock/reset domains that group elements with common clock and reset signals. The reset circuitry for one of these domains is illustrated in Figure 10-5. This circuit provides controllable skews on the reset nets within the design. The following UCF syntax identifies the relevant reset logic and groups them together.
PAGE 97
-- DISCONTINUED PRODUCT -R Required Constraints GMII Input Setup/Hold Timing Figure 9-1 and Table 9-1 illustrate the setup and hold time window for the input GMII signals. This is the worst-case data valid window presented to the FPGA device pins. GMII_RX_CLK GMII_RXD[7:0], GMII_RX_DV, GMII_RX_ER tSETUP tHOLD Figure 9-1: Input GMII Timing Observe that there is a 2 ns data valid window which is presented across the GMII input bus. This must be correctly sampled by the FPGA devices.
PAGE 98
-- DISCONTINUED PRODUCT -R Chapter 9: Constraining the Core The fixed phase-shift is applied to the DCM using the following UCF syntax: INST *gmii_interface/gmii_rxc_dcm CLKOUT_PHASE_SHIFT = FIXED; INST *gmii_interface/gmii_rxc_dcm PHASE_SHIFT = 0; The value of PHASE_SHIFT is preconfigured in the example designs to meet the setup and hold constraints for the example GMII pinout in the particular device.
PAGE 99
-- DISCONTINUED PRODUCT -R Required Constraints Understanding Timing Reports for GMII Setup/Hold Timing Non-Virtex-5 devices Setup and Hold results for the GMII input bus can be found in the data sheet section of the Timing Report. The results are self-explanatory and it is easy to see how they relate to Figure 9-1. Following is an example for the GMII report from a Virtex-4 device. The implementation requires 1.531 ns of setup—this is less than the 2 ns required so there is some slack.
PAGE 100
-- DISCONTINUED PRODUCT -R Chapter 9: Constraining the Core Data Sheet report: ----------------All values displayed in nanoseconds (ns) Setup/Hold to clock gmii_rx_clk ------------+------------+------------+------------------+--------+ | Setup to | Hold to | | Clock | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | ------------+------------+------------+------------------+--------+ gmii_rx_dv | 1.955(R)| -0.017(R)| gmii_rx_clk_bufg | 0.000| gmii_rx_er | 1.962(R)| -0.
PAGE 101
-- DISCONTINUED PRODUCT -R Required Constraints The implementation requires 7.554 ns of hold. Figure 9-2 illustrates that this represents a figure of -0.446 ns relative to the following rising edge of the clock (since the IDELAY has acted to delay the clock by an entire period when measured from the input flip-flop). This is less than the 0 ns required so there is slack. GMII_RX_CLK GMII_RXD[7:0], GMII_RX_DV GMII_RX_ER 8 ns -6.134 ns tSETUP = 8 - 6.134 = 1.866 ns tHOLD = 7.554 - 8 = -0.446 ns 7.
PAGE 102
-- DISCONTINUED PRODUCT -R Chapter 9: Constraining the Core The RGMII v2.0 is a 1.5 volt signal-level interface. The 1.5 volt HSTL Class I SelectIO standard is used for RGMII interface pins. Use the following constraints with the device IO Banking rules. The IO slew rate is set to fast to ensure that the interface can meet setup and hold times.
PAGE 103
-- DISCONTINUED PRODUCT -R Required Constraints INST "rgmii_rxd" TNM = IN_RGMII; INST "rgmii_rx_ctl" TNM = IN_RGMII; TIMEGRP "DDR_RISING" = FFS; TIMEGRP "DDR_FALLING" = FALLING FFS; TIMEGRP "IN_RGMII" OFFSET = IN 1.1 ns VALID 2.2 ns BEFORE "rgmii_rxc" TIMEGRP "DDR_RISING"; TIMEGRP "IN_RGMII" OFFSET = IN -2.9 ns VALID 2.
PAGE 104
-- DISCONTINUED PRODUCT -R Chapter 9: Constraining the Core INST *rgmii_interface/delay_rgmii_tx_clk IDELAY_TYPE = “FIXED”; INST *rgmii_interface/delay_rgmii_tx_clk ODELAY_VALUE = 25; INST *rgmii_interface/delay_rgmii_tx_clk DELAY_SRC = “O”; INST *rgmii_interface/delay_rgmii_rx_ctl IDELAY_TYPE = “FIXED”; INST *rgmii_interface/delay_rgmii_rx_ctl IDELAY_VALUE = 20; INST *rgmii_interface/delay_rgmii_rx_ctl DELAY_SRC = “I”; The value of IDELAY_VALUE is preconfigured in the example designs to meet the setup a
PAGE 105
-- DISCONTINUED PRODUCT -R Required Constraints Understanding Timing Reports for RGMII Setup/Hold timing Non-Virtex-5 Devices Setup and Hold results for the RGMII input bus can be found in the data sheet section of the Timing Report. The results are self-explanatory and it is easy to see how they relate to Figure 9-3. Following is an example for the RGMII report from a Virtex-4 device. Each Input lists two sets of values—one corresponding to the –ve edge of the clock and one to the +ve edge.
PAGE 106
-- DISCONTINUED PRODUCT -R Chapter 9: Constraining the Core Data Sheet report: ----------------All values displayed in nanoseconds (ns) Setup/Hold to clock rgmii_rxc ------------+------------+------------+------------------+--------+ | Setup to | Hold to | | Clock | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | ------------+------------+------------+------------------+--------+ rgmii_rx_ctl| 0.810(R)| 0.933(R)| rgmii_rx_clk_bufg| 0.000| | -3.214(F)| 4.959(F)| rgmii_rx_clk_bufg| 4.
PAGE 107
-- DISCONTINUED PRODUCT -R Required Constraints This is less than the 1 ns required, so there is slack. Equally for the –ve edge, we have –11.179 ns of setup—this edge is at time 12 ns and therefore this equates to a setup of 0.821 ns. The implementation requires 8.893 ns of hold to the +ve edge. Figure 9-4 illustrates that this represents 0.893 ns relative to the following rising edge of the clock (since the IDELAY has acted to delay the clock by an entire period when measured from the input flip-flop).
PAGE 108
-- DISCONTINUED PRODUCT -R 108 Chapter 9: Constraining the Core www.xilinx.com 1-Gigabit Ethernet MAC v8.
PAGE 109
-- DISCONTINUED PRODUCT -R Chapter 10 Clocking and Resetting This chapter describes clock management considerations that are associated with implementing the GEMAC core. It describes the clock management logic for all implementations of the core and how clock management logic can be shared across multiple instantiations of the core. The reset circuitry within the core is also described.
PAGE 110
-- DISCONTINUED PRODUCT -R Chapter 10: Clocking and Resetting With RGMII Standard Clocking Scheme Figure 10-2 illustrates the clock management used with an external RGMII interface. All clocks illustrated have a frequency of 125 MHz. The gtx_clk clock must be provided to the GEMAC core. This is a high-quality clock that satisfies IEEE 802.3-2005 requirements.
PAGE 111
-- DISCONTINUED PRODUCT -R Multiple Cores Note: Although not illustrated, if the optional Management Interface is used, host_clk can also be shared between cores.
PAGE 112
-- DISCONTINUED PRODUCT -R Chapter 10: Clocking and Resetting DCM BUFG CLK_0 IBUFG gtx_clk BUFG CLK_90 BUFG 1-Gigabit Ethernet MAC Core gtx_clk gmii_rx_clk DCM CLK_0 IBUFG rgmii_rxc1 RGMII Tx Logic RGMII Rx Logic BUFG 1-Gigabit Ethernet MAC Core gtx_clk DCM CLK_0 gmii_rx_clk IBUFG rgmii_rxc2 RGMII Rx Logic RGMII Tx Logic Figure 10-4: Clock Management Logic with External RGMII (Multiple Cores) Reset Conditions Internally, the core is divided up into clock/reset domains that group toget
PAGE 113
-- DISCONTINUED PRODUCT -R Chapter 11 Interfacing to Other Cores Ethernet 1000Base-X PCS/PMA or SGMII Core The GEMAC core can be integrated in a single device with the Ethernet 1000BASE-X PCS/PMA or SGMII core to extend core functionality to provide the following: 1000BASE-X Physical Coding Sublayer (PCS) logic designed to the IEEE 802.3 specification with either: • 1000BASE-X Physical Medium Attachment (PMA) using a device-specific RocketIO™ transceiver.
PAGE 114
-- DISCONTINUED PRODUCT -R Chapter 11: Interfacing to Other Cores Integration to Provide 1000BASE-X PCS with TBI Figure 11-1 illustrates the connections and clock management logic required to interface the GEMAC core to the Ethernet 1000BASE-X PCS/PMA or SGMII core (when used in 1000BASE-X mode with the parallel TBI). It depicts the following: • Direct internal connections are made between the GMII interfaces of the two cores.
PAGE 115
-- DISCONTINUED PRODUCT -R Ethernet 1000Base-X PCS/PMA or SGMII Core Integration to Provide 1000BASE-X PCS and PMA using a RocketIO Transceiver Virtex-4 Devices Figure 11-2 illustrates the connections and clock management logic required to interface the GEMAC core to the Ethernet 1000BASE-X PCS/PMA or SGMII core (when used in 1000BASE-X mode with PMA using the device-specific RocketIO MGT transceiver.
PAGE 116
-- DISCONTINUED PRODUCT -R Chapter 11: Interfacing to Other Cores Figure 11-2 illustrates the following: 116 • Direct internal connections are made between the GMII interfaces between the two cores. • If the GEMAC has been generated with the optional Management Interface, the MDIO port can be connected up to that of the Ethernet 1000BASE-X PCS/PMA or SGMII core to access its embedded configuration and status registers. See “Using the Optional Management Interface.
PAGE 117
-- DISCONTINUED PRODUCT -R Ethernet 1000Base-X PCS/PMA or SGMII Core Virtex-5 LXT and SXT Devices Figure 11-3 illustrates the connections and clock management logic required to interface the GEMAC core to the Ethernet 1000BASE-X PCS/PMA or SGMII core (when used in 1000BASE-X mode with PMA using the device-specific RocketIO transceiver).
PAGE 118
-- DISCONTINUED PRODUCT -R Chapter 11: Interfacing to Other Cores • Due to the embedded Receiver Elastic Buffer in the Ethernet 1000BASE-X PCS/PMA or SGMII core, the entire GMII is synchronous to a single clock domain. For this reason, userclk2 is used as the 125 MHz reference clock for both cores and the transmitter and receiver logic of the GEMAC core now operate in the same clock domain.
PAGE 119
-- DISCONTINUED PRODUCT -R Ethernet Statistics Core Features of this configuration include: • Direct internal connections are made between the GMII interfaces between the two cores. • If the GEMAC has been generated with the optional Management Interface, the MDIO port can be connected up to that of the Ethernet 1000BASE-X PCS/PMA or SGMII core to access its embedded configuration and status registers. See “Using the Optional Management Interface.
PAGE 120
-- DISCONTINUED PRODUCT -R Chapter 11: Interfacing to Other Cores Figure 11-5 illustrates connecting the Ethernet Statistics core to the MAC.
PAGE 121
-- DISCONTINUED PRODUCT -R Ethernet Statistics Core The management interfaces of the two cores can be shared by avoiding bus conflict, as follows: • Selecting a different address range for the statistics to that of the MAC configuration registers. This is achieved by setting host_addr[9] to logic 0 when reading from the statistics and logic 1 when writing and reading to the MAC configuration registers.
PAGE 122
-- DISCONTINUED PRODUCT -R 122 Chapter 11: Interfacing to Other Cores www.xilinx.com 1-Gigabit Ethernet MAC v8.
PAGE 123
-- DISCONTINUED PRODUCT -R Chapter 12 Implementing Your Design This chapter describes how to simulate and implement your design containing the GEMAC core. Pre-implementation Simulation A unit delay structural model of the GEMAC core netlist is provided as a CORE Generator™ output file. This can be used for simulation of the block in the design phase of the project.
PAGE 124
-- DISCONTINUED PRODUCT -R Chapter 12: Implementing Your Design To synthesize the design, run: $ xst -ifn top_level_module_name.scr See the XST User Guide for more information on creating project and synthesis script files, and running the xst program. XST—Verilog A module declaration for the GEMAC core is provided in the CORE Generator project directory: /example_design/_mod.v Use this module to help instance the GEMAC core into your Verilog source.
PAGE 125
-- DISCONTINUED PRODUCT -R Post-Implementation Simulation Placing-and-Routing the Design Execute the par command to place-and-route your design logic components (mapped physical logic cells) contained within an NCD file in accordance with the layout and timing requirements specified within the PCF file. The par command outputs the placed and routed physical design to an NCD file. An example of the par command is: $ par top_level_module_name_map.ncd top_level_module_name.ncd \ top_level_module_name.
PAGE 126
-- DISCONTINUED PRODUCT -R Chapter 12: Implementing Your Design Using the Model For information about setting up your simulator to use the pre-implemented model, see the Xilinx Synthesis and Verification Design Guide included in your Xilinx software installation. Other Implementation Information For more information about using the Xilinx implementation tool flow, including command line switches and options, see the Xilinx ISE® software manuals. 126 www.xilinx.com 1-Gigabit Ethernet MAC v8.
PAGE 127
-- DISCONTINUED PRODUCT -R Appendix A Using the Client-Side FIFO The example design provided with the GEMAC core contains a FIFO used on the clientside of the core. The source code for the FIFO is provided, and may be used and adjusted for user applications. The 10 Mbps/100 Mbps/1 Gbps Ethernet FIFO is designed for use with the GEMAC and Tri-Mode Ethernet MAC (TEMAC) cores. The FIFO directly interfaces to the MAC client interface providing a buffer between the MAC and the user’s logic.
PAGE 128
-- DISCONTINUED PRODUCT -R Appendix A: Using the Client-Side FIFO Interfaces Transmit FIFO Table A-1 describes the transmit FIFO client interface. For more information on the MAC client interface, see “Transmitting Outbound Frames,” on page 47. Table A-1: Transmit FIFO Client Interface Direction Clock Domain tx_clk Input N/A Transmit clock used by MAC. tx_reset Input tx_clk Synchronous reset. tx_enable Input tx_clk Clock enable for tx_clk. Tie to logic 1 when using GEMAC.
PAGE 129
-- DISCONTINUED PRODUCT -R Interfaces Receive FIFO Table A-3 describes the receive FIFO client interface. For more information on the MAC client interface, see “Receiving Inbound Frames,” on page 39.
PAGE 130
-- DISCONTINUED PRODUCT -R Appendix A: Using the Client-Side FIFO Overview of LocalLink Interface Data Flow Data is transferred on the LocalLink interface from source to destination, with the flow being governed by the four active low control signals sof_n, eof_n, src_rdy_n, and dst_rdy_n. The flow of data is controlled by the src_rdy_n and dst_rdy_n signals. Only when these signals are asserted simultaneously is data transferred from source to destination.
PAGE 131
-- DISCONTINUED PRODUCT -R Functional Operation Functional Operation Clock Requirements The FIFO is designed to work with rx_clk and tx_clk running at MAC clock speeds up to 125 MHz. The rx_ll_clock should be no slower than the rx_clk. The tx_ll_clock should be no slower than the clock on the transmitter client interface divided by 2. For this reason, it is suggested that the rx_ll_clock and tx_ll_clock are always 125 MHz or faster.
PAGE 132
-- DISCONTINUED PRODUCT -R Appendix A: Using the Client-Side FIFO Verilog The compiler directive FULL_DUPLEX_ONLY is defined to allow for removal of logic and performance constraints that are necessary only in half-duplex operation, that is, when using with the Tri-Mode Ethernet MAC core. This directive can always be defined when the FIFO is used with the GEMAC. The FIFO has two signal inputs specific to half-duplex operation, tx_collision and tx_retransmit.
PAGE 133
-- DISCONTINUED PRODUCT -R Appendix B Core Verification, Compliance, and Interoperability The GEMAC core has been verified with extensive simulation and hardware testing. Verification by Simulation A highly parameterizable transaction-based test bench (not part of the core deliverables) was used to test the core.
PAGE 134
-- DISCONTINUED PRODUCT -R 134 Appendix B: Core Verification, Compliance, and Interoperability www.xilinx.com 1-Gigabit Ethernet MAC v8.
PAGE 135
-- DISCONTINUED PRODUCT -R Appendix C Calculating DCM Phase-Shifting DCM Phase-Shifting A DCM is used in the receiver clock path to meet the input setup and hold requirements when using the core with an RGMII (see “Implementing External RGMII,” on page 66) and with an external GMII implementation in Spartan®-3, Spartan-3E, Spartan-3A and Virtex®-4 devices (see “Spartan-3, Spartan-3E, Spartan-3A and Virtex-4 Devices,” on page 63.
PAGE 136
-- DISCONTINUED PRODUCT -R Appendix C: Calculating DCM Phase-Shifting Perform a complete sweep of phase-shift settings during your initial system test. Use only positive (0 to 255) phase-shift settings, and use a test range that covers a range of no less than 128, corresponding to a total 180 degrees of clock offset. This does not imply that 128 phase-shift values must be tested; increments of 4 (52, 56, 60, etc.) correspond to roughly one DCM tap, and consequently provide an appropriate step size.
PAGE 137
-- DISCONTINUED PRODUCT -R Appendix D Core Latency Transmit Path Latency As measured from a data octet accepted on tx_data[7:0] of the transmitter client-side interface, until that data octet appears on gmii_txd[7:0] of the physical side GMII style interface, the latency through the core in the transmit direction is 9 clock periods of gtx_clk.
PAGE 138
-- DISCONTINUED PRODUCT -R 138 Appendix D: Core Latency www.xilinx.com 1-Gigabit Ethernet MAC v8.