Specifications

414 www.xilinx.com Development System Reference Guide
R
period
The period is the number of steps in a clock pattern multiplied by the
step size.
physical annotation
Physical annotation uses just the .ncd file. In this mode, a timing
simulation model is generated from the physical device components.
PIM
Physically Implemented Module
pin
A pin can be a symbol pin or a package pin. A package pin is a
physical connector on an integrated circuit package that carries
signals into and out of an integrated circuit. A symbol pin, also
referred to as an instance pin, is the connection point of an instance to
a net.
PIP (programmable interconnect points)
Programmable interconnect points, or PIP, provide the routing paths
used to connect the inputs and outputs of IOBs and CLBs into logic
networks.
A PIP is made of a CMOS transistor, which you can turn on and off to
activate the PIP.
placing
Placing is the process of assigning physical device cell locations to the
logic in a design.
PLD
A Programmable Logic Device (PLD), is composed of two types of
gate arrays: the AND array and the OR array, thus providing for sum
of products algorithmic representations. PLDs include three distinct
types of chips: PROMs, PALs, and PLAs. The most flexible device is
the PLA (programmable logic array) in which both the AND and OR
gate arrays are programmable. In the PROM device, only the OR gate
array is programmable. In the PAL device, only the AND gate array is
programmable. PLDs are programmed by blowing the fuses along the
paths that must be disconnected.
FPGAs and CPLDs are classes of PLDs.
post-synthesis simulation
This type of simulation is usually done after the HDL code has been
expanded into gates. Post-synthesis simulation is similar to behavioral
simualtion since design behavior is being checked. The difference is
that in post-synthesis simulation the synthesis tool’s results are being
checked. If post-synthesis and behavioral simulation match, then the
HDL synthesis tool has interpreted the HDL code correctly.