Specifications

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combinatorial logic
Combinatorial logic refers to any primitives with the exception of
storage elements such as flip-flops.
compiler
A compiler is a language interpreter. The Synopsys compiler
interprets HDL and makes concurrent process implementations for
target architectures.
component
A component is an instantiation or symbol reference from a library of
logic elements that can be placed on a schematic.
configuration
Configuration is the process of loading design-specific bitstreams into
one or more FPGA devices to define the functional operation of the
logical blocks, their interconnections, and the chip I/O.
This concept also refers to the configuration of a design directory for a
particular design library.
constraints
Constraints are specifications for the implementation process. There
are several categories of constraints: routing, timing, area, mapping,
and placement constraints.
Using attributes, you can force the placement of logic (macros) in
CLBs, the location of CLBs on the chip, and the maximum delay
between flip-flops. PAR does not attempt to change the location of
constrained logic.
constraints file
A constraints file specifies constraints (location and path delay)
information in a textual form. An alternate method is to place
constraints on a schematic.
contention
Contention is the state in which multiple conflicting outputs drive the
same net.
counter
A counter is a circuit, composed of registers, that counts pulses, often
reacting or causing a reaction to a predetermined pulse or series of
pulses. Also called a divider, sometimes accumulator.