Specifications
Development System Reference Guide www.xilinx.com 319
NetGen Simulation Flow
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NetGen Supported Flows
NetGen can be described as having three fundamental flows: simulation, equivalency 
checking, and third-party static timing analysis. This chapter contains flow-specific 
sections that detail the use and features of NetGen support flows and describe any sub-
flows. For example, the simulation flow includes two flows types: functional simulation 
and timing simulation.
Each flow-specific section includes command line syntax, input files, output files, and 
available command line options for each NetGen flow. 
NetGen syntax is based on the type of NetGen flow you are running. For details on NetGen 
flows and syntax, refer to the flow-specific sections that follow. 
Valid netlist flows are:
simulation [sim]— generates a simulation netlist for functional simulation or timing 
simulation. For this netlist type, you must specify the output file type as Verilog or 
VHDL with the –ofmt option. 
netgen –sim [options]
equivalence [ecn]— generates a Verilog-based equivalence checking netlist. For this 
netlist type, you must specify a tool name after the –ecn option. Possible tool names for 
this netlist type are conformal or formality. 
netgen –ecn conformal|formality [options]
static timing analysis [sta]—generates a Verilog netlist for static timing analysis.
netgen –sta [options]
NetGen Simulation Flow
Within the NetGen Simulation flow, there are two sub-flows: functional simulation and 
timing simulation. The functional simulation flow may be used for UNISIM-based or 
SIMPRIM-based netlists, based on the input file. An input NGC file will generate a 
UNISIM-based netlist for functional simulation. An input NGD file will generate a 
SIMPRIM-based netlist for functional simulation. Similarly, timing simulation can be 
broken down further to post-map timing simulation and post-par timing simulation, both 
of which use SIMPRIM-based netlists. 
Note:
NetGen does not list LOC parameters when an NGD file is used as input. In this case, 
“UNPLACED” is reported as the default value for LOC parameters. 
Options for the NetGen Simulation flow (and sub-flows) can be viewed by running 
netgen -h sim from the command line. 
NetGen Functional Simulation Flow
This section describes the functional simulation flow, which is used to translate NGC and 
NGD files into Verilog or VHDL netlists. 
When you enter an NGC file as input on the NetGen command line, NetGen invokes the 
functional simulation flow to produce a UNISIM-based netlist. Similarly, when you enter 
an NGD file as input on the NetGen command line, NetGen invokes the functional 
simulation flow to produce a SIMPRIM-based netlist. You must also specify the type of 
netlist you want to create: Verilog or VHDL.










