Specifications

Development System Reference Guide www.xilinx.com 237
TRACE Reports
R
The following sample verbose report (verbose.twr) represents the output generated with
this TRACE command:
trce –v 1 ramb16_s1.ncd clkperiod.pcf –o verbose_report.twr
------------------------------------------------------------------
Xilinx TRACE
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
trce -v 1 ramb16_s1.ncd clkperiod.pcf -o verbose_report.twr
Design file: ramb16_s1.ncd
Physical constraint file: clkperiod.pcf
Device,speed: xc2v250,-5 (ADVANCED 1.84 2001-05-09)
Report level: verbose report, limited to 1 item per constraint
------------------------------------------------------------------
==================================================================
Timing constraint: TS01 = PERIOD TIMEGRP "clk" 10.333ns ;
0 items analyzed, 0 timing errors detected.
------------------------------------------------------------------
==================================================================
Timing constraint: OFFSET = IN 3.0 ns AFTER COMP "clk" TIMEGRP "rams" ;
18 items analyzed, 0 timing errors detected.
Maximum allowable offset is 9.224ns.
------------------------------------------------------------------
Slack: 6.224ns (requirement - (data path - clock path
- clock arrival))
Source: ssr
Destination: RAMB16.A
Destination Clock: CLK rising at 0.000ns
Requirement: 7.333ns
Data Path Delay: 2.085ns (Levels of Logic = 2)
Clock Path Delay: 0.976ns (Levels of Logic = 2)
Data Path: ssr to RAMB16.A
Location Delay type Delay(ns)
Physical Resource
Logical Resource(s)
-------------------------------------------------------
IOB.I Tiopi
0.551 ssr
ssr
I$36
RAM16.SSRA net e 0.100 N$9
(fanout=1)
RAM16.CLKA Tbrck 1.434 RAMB16
RAMB16.A
-------------------------------------------------------
Total 2.085ns (1.985ns logic, 0.100ns
route)
(95.2% logic, 4.8%
route)