Specifications

232 www.xilinx.com Development System Reference Guide
Chapter 12: TRACE
R
Timing summary:
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Timing errors: 0 Score: 0
Constraints cover 20 paths, 21 nets, and 21 connections (100.0%
coverage)
Design statistics:
Minimum period: 2.840ns (Maximum frequency: 352.113MHz)
Maximum combinational path delay: 6.063ns
Maximum net delay: 0.001ns
Analysis completed Wed Mar 8 14:52:30 2000
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Summary Report (With a Physical Constraints File Specified)
The following sample summary report represents the output of this TRACE
command:
trce –o summary1.twr ramb16_s1.ncd clkperiod.pcf
The name of the report is summary1.twr. The timing analysis represented
in the file were performed by referring to the constraints in the file
clkperiod.pcf.
------------------------------------------------------------------
Xilinx TRACE
Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
Design file: ramb16_s1.ncd
Physical constraint file: clkperiod.pcf
Device,speed: xc2v250,-6
Report level: summary report
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Asterisk (*) preceding a constraint indicates it was not met.
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Constraint | Requested | Actual | Logic
| | | Levels
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TS01 = PERIOD TIMEGRP "clk" 10.0ns| | |
------------------------------------------------------------------
OFFSET = IN 3.0 ns AFTER COMP
"clk" TIMEG | 3.000ns | 8.593ns |2
RP "rams"
------------------------------------------------------------------
* TS02 = MAXDELAY FROM TIMEGRP
"rams" TO TI | 6.000ns | 6.063ns |2
MEGRP "pads" 6.0 ns| | |
------------------------------------------------------------------
1 constraint not met.
Data Sheet report:
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All values displayed in nanoseconds (ns)