Specifications

ManualsBrandsWorth Data ManualsBarcode Reader520-RF

Si4730/31/34/35-D60

BROADCAST AM/FM/SW/LW RADIO RECEIVER

Features

Applications

Description

The Si473x-D60 digital CMOS AM/FM radio receiver IC integrates the complete

broadcast tuner and receiver function from antenna input to digital audio output.

The device leverages the Silicon Labs broadcast proven digital low-IF

architecture, enabling a cost-effective, digital audio platform for consumer

electronic applications with high TDMA noise immunity, superior radio

performance, and high fidelity audio power amplification.

Functional Block Diagram

 Worldwide FM band support

(64–108 MHz)

 Worldwide AM band support

(520–1710 kHz)

 SW band support (Si4734/35)

(2.3–26.1 MHz)

 LW band support (Si4734/35)

(153–279 kHz)

 Excellent real-world performance

 Integrated VCO

 Advanced AM/FM seek tuning

 Automatic frequency control (AFC)

 Automatic gain control (AGC)

 Digital FM stereo decoder

 Programmable de-emphasis

 Advanced Audio Processing

 Seven selectable AM channel filters

 AM/FM/SW/LW digital tuning

 EN55020 compliant

 No manual alignment necessary

 Programmable reference clock

 Adjustable soft mute control

 RDS/RBDS processor (Si4731/35)

 Digital audio out

 2-wire and 3-wire control interface

 Integrated LDO regulator

 Wide range of ferrite loop sticks and

air loop antennas supported

 QFN and SSOP packages

RoHS compliant

 Table and portable radios

 Mini/micro systems

 CD/DVD and Blu-ray players

 Stereo boom boxes

 Modules for consumer electronics

 Clock radios

 Mini HiFi and docking stations

 Entertainment systems

ADC

Si473x-D60

DSP

DAC

LOUT

ROUT

AFC

GPO/DCLK

LDO

2.7~5.5 V (QFN)

2.0~5.5 V (SSOP)

RDS

(Si4731/

35)

AMI

1.62 - 3.6 V

SEN

CONTROL

INTERFACE

SCLK

LNA

AGC

LNA

AGC

GND

ADC

Mux

DAC

LOW-IF

SDIO

RST

DIGITAL

AUDIO

DFS

DOUT

RCLK

AM / LW

ANT

RFGND

FMI

FM / SW

ANT

This product, its features, and/or its

architecture is covered by one or more of

the following patents, as well as other

patents, pending and issued, both

foreign and domestic: 7,127,217;

7,272,373; 7,272,375; 7,321,324;

7,355,476; 7,426,376; 7,471,940;

7,339,503; 7,339,504.

Ordering Information:

See page 31.

Pin Assignments

Si473x-D60(SSOP)

Si473x-D60 (QFN)

GND

PAD

17181920

7 8 9

GPO2/[INT]

DOUT

LOUT/[DFS]

ROUT/[DOUT]

GNDRST

AMI

RCLK

SDIO

FMI

RFGND

GPO3/[DCLK]

GPO1

DFS

SCLK

SEN

LOUT/[DFS]

ROUT/[DOUT]

DBYP

GPO2/[INT]

GPO3/[DCLK]

DOUT

DFS

GPO1

SDIO

RCLK

SEN

FMI

RFGND

SCLK

GND

RST

GND

AMI

Summary of content (42 pages)

PAGE 1
Si4730/31/34/35-D60 B ROADCAST AM/FM/SW/LW R ADIO R ECEIVER Features                 Ordering Information: See page 31.
PAGE 2
Si4730/31/34/35-D60 2 Rev. 1.
PAGE 3
Si4730/31/34/35-D60 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.1. QFN Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2. SSOP Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
Si4730/31/34/35-D60 9. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 9.1. Si473x-D60 Top Marking (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.2. Top Marking Explanation (QFN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.3. Si473x-D60 Top Marking (SSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.4.
PAGE 5
Si4730/31/34/35-D60 1. Electrical Specifications Table 1. Recommended Operating Conditions1 Parameter Symbol Test Condition Min Typ Max Unit Analog Supply Voltage VA 2.72 — 5.5 V Digital and I/O Supply Voltage VD 1.62 — 3.6 V Power Supply Powerup Rise Time VDDRISE 10 — — µs Interface Power Supply Powerup Rise Time VIORISE 10 — — µs TA –20 25 85 C Ambient Temperature Notes: 1. All minimum and maximum specifications apply across the recommended operating conditions.
PAGE 6
Si4730/31/34/35-D60 Table 2. DC Characteristics (VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max — 8.2 9.5 — 10.5 13.5 — 18.5 21.5 Unit FM Mode VAQFN Supply Current IFMVA VDQFN Supply Current IFMVD VASSOP Supply Current IFMVA VDSSOP Supply Current IFMVD — 0.15 0.6 VAQFN Supply Current IFMVA — 9.1 10.3 VDQFN Supply Current IFMVD — 9.9 12.8 VASSOP Supply Current IFMVA — 19.1 21.3 VDSSOP Supply Current IFMVD 0.
PAGE 7
Si4730/31/34/35-D60 Table 3. Reset Timing Characteristics1,2,3 (VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Min Typ Max Unit tSRST 100 — — µs GPO1, GPO2/INT Hold from RST tHRST 30 — — ns RST Pulse Release time before VDD/VIO turn off tRRST 30 — — ns RST Pulse Width and GPO1, GPO2/INT Setup to RST Important Notes: 1.
PAGE 8
Si4730/31/34/35-D60 Table 4. 2-Wire Control Interface Characteristics1,2,3 (VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit SCLK Frequency fSCL 0 — 400 kHz SCLK Low Time tLOW 1.3 — — µs SCLK High Time tHIGH 0.6 — — µs SCLK Input to SDIO  Setup (START) tSU:STA 0.6 — — µs SCLK Input to SDIO  Hold (START) tHD:STA 0.
PAGE 9
Si4730/31/34/35-D60 SCLK SDIO tSU:STA tHD:STA tLOW START tr:IN tHIGH tr:IN tf:IN tSP tSU:STO tBUF 70% 30% 70% 30% tf:IN, tf:OUT tHD:DAT tSU:DAT STOP START Figure 2. 2-Wire Control Interface Read and Write Timing Parameters SCLK A6-A0, R/W SDIO START ADDRESS + R/W D7-D0 ACK DATA D7-D0 ACK DATA ACK STOP Figure 3. 2-Wire Control Interface Read and Write Timing Diagram Rev. 1.
PAGE 10
Si4730/31/34/35-D60 Table 5. 3-Wire Control Interface Characteristics (VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit SCLK Frequency fCLK 0 — 2.
PAGE 11
Si4730/31/34/35-D60 Table 6. Digital Audio Interface Characteristics (VA = 2.7 to 5.5 V, VD = 1.62 to 3.
PAGE 12
Si4730/31/34/35-D60 Table 7. FM Receiver Characteristics1,2 (VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Min Typ Max Unit 76 — 108 MHz (S+N)/N = 26 dB — 2.2 3.5 µV EMF f = 2 kHz, RDS BLER < 5% — 10 — µV EMF 3 4 5 k 4 5 6 pF 100 105 — dBµV EMF m = 0.
PAGE 13
Si4730/31/34/35-D60 Table 7. FM Receiver Characteristics1,2 (Continued) (VA = 2.7 to 5.5 V, VD = 1.62 to 3.
PAGE 14
Si4730/31/34/35-D60 Table 8. 64–75.9 MHz Input Frequency FM Receiver Characteristics1,2,3 (VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Min Typ Max Unit 64 — 75.9 MHz — 3.5 — µV EMF 3 4 5 k 4 5 6 pF — 105 — dBµV EMF m = 0.
PAGE 15
Si4730/31/34/35-D60 Table 9. AM/SW/LW Receiver Characteristics1,2 (VA = 2.7 to 5.5 V, VA = 1.62 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit fRF Long Wave (LW) 153 — 279 kHz Medium Wave (AM) 520 — 1710 kHz Short Wave (SW) 2.3 — 26.1 MHz (S+N)/N = 26 dB — 25 35 µV EMF THD < 8% — 300 — mVRMS ∆VDD = 100 mVRMS, 100 Hz — 40 — dB Audio Output Voltage3,7 54 60 67 mVRMS 3,4,7 — 60 — dB — 0.1 0.
PAGE 16
Si4730/31/34/35-D60 Table 10. Reference Clock and Crystal Characteristics (VA = 2.7 to 5.5 V, VD = 1.62 to 3.6 V, TA = –20 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit 31.130 32.768 40,000 kHz –100 — 100 ppm 1 — 4095 31.130 32.768 34.406 kHz — 32.768 — kHz –100 — 100 ppm Board Capacitance — — 3.
PAGE 17
Si4730/31/34/35-D60 Table 12. Absolute Maximum Ratings1,2 Parameter Symbol Value Unit Analog Supply Voltage VA –0.5 to 5.8 V Digital and I/O Supply Voltage VD –0.5 to 3.9 V Input Current3 IIN 10 mA 3 VIN –0.3 to (VIO + 0.3) V Operating Temperature TOP –40 to 95 C Storage Temperature TSTG –55 to 150 C 0.4 Vpk Input Voltage RF Input Level4 Notes: 1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded.
PAGE 18
Si4730/31/34/35-D60 2. Typical Application Schematic 2.1. QFN Typical Application Schematic 2SWLRQDO 'LJLWDO $XGLR 2XW 2302'( [% [% & *32 *32 ,17 5 *32 '&/. 5287 6L [ *1' /287 5287 WR 9 & 9$ 9' 9$ 5&/. '287 ')6 *32 '&/. /287 ' ')6 5 '287 567% 6(1% $0, & 5)*1' 6',2 / )0, *32 ,17 1& 6&/. )0 $QWHQQD 1& & *32 5 WR 9 & 567% 9' 5&/. 6',2 6&/.
PAGE 19
Si4730/31/34/35-D60 2.2. SSOP Typical Application Schematic 2SWLRQDO 'LJLWDO $XGLR 2XW 2302'( [% [% & *32 '&/. 5 5 *32 ,17 *32 & )0 $QWHQQD '287 /287 ')6 5287 *32 '&/. '%<3 *32 ,17 *32 1& 1& & 9$ 9' 5&/. )0, 5)*1' 1& / ' ')6 5 6L [ '287 6',2 6&/. 6(1% 567% 5287 & WR 9 6&/. 6(1% *1' & 6',2 WR 9 5&/.
PAGE 20
Si4730/31/34/35-D60 3. Bill of Materials 3.1. QFN/SSOP Bill of Materials Table 13. Si473x-D60 QFN/SSOP Bill of Materials Component(s) Value/Description Supplier C1 Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R Murata C2 Coupling capacitor, 1 nF, ±20%, Z5U/X7R Murata C3 Coupling capacitor, 0.
PAGE 21
Si4730/31/34/35-D60 4. Functional Description 4.1. Overview FM / SW ANT Si473x-D 60 RDS (Si4731/ 35) FM I LN A AMI ADC LD O DAC LO U T C O N TR O L IN TER FA C E A FC SEN VD 1.62 - 3.6 V RST Mux VA GND ROUT D SP RCLK + AGC DAC SDIO 2.7~5.5 V (Q FN ) 2.0~5.5 V (SSO P ) LN A SCLK R FG N D ADC M ux D FS G PO /D C LK LO W -IF AGC A M / LW ANT DOUT D IG ITA L A U D IO Figure 7.
PAGE 22
Si4730/31/34/35-D60 4.2. Operating Modes The Si473x-D60 operates in either an FM receive or AM receive modes. In FM mode, radio signals are received on FMI and processed by the FM front-end circuitry. In AM mode, radio signals are received on AMI and processed by the AM front-end circuitry. In addition to the receiver mode, there is a clocking mode to choose to clock the Si473x-D60 from a reference clock or crystal.
PAGE 23
Si4730/31/34/35-D60 4.7. Digital Audio Interface 4.7.2. Audio Sample Rates The digital audio interface operates in slave mode and supports a variety of MSB-first audio data formats including I2S and left-justified modes. The interface has three pins: digital data input (DIN), digital frame synchronization input (DFS), and a digital bit synchronization input clock (DCLK). The Si473x-D60 supports a number of industry-standard sampling rates including 32, 44.1, and 48 kHz.
PAGE 24
Si4730/31/34/35-D60 (OFALL = 1) INVERTED DCLK (OFALL = 0) DCLK LEFT CHANNEL DFS I2S (OMODE = 0000) RIGHT CHANNEL 1 DCLK 1 DCLK 1 DOUT 2 n-2 3 n-1 MSB n 1 LSB MSB 2 n-2 3 n-1 n LSB Figure 8. I2S Digital Audio Format (OFALL = 1) INVERTED DCLK (OFALL = 0) DCLK DFS LEFT CHANNEL RIGHT CHANNEL Left-Justified (OMODE = 0110) 1 DOUT 2 3 n-2 n-1 MSB n 1 LSB MSB 2 n-2 3 n-1 n LSB Figure 9.
PAGE 25
Si4730/31/34/35-D60 4.9. Received Signal Qualifiers The output of the FM demodulator is a stereo multiplexed (MPX) signal. The MPX standard was developed in 1961, and is used worldwide. Today's MPX signal format consists of left + right (L+R) audio, left – right (L–R) audio, a 19 kHz pilot tone, and RDS/RBDS data as shown in Figure 11 below. The quality of a tuned signal can vary depending on many factors including environmental conditions, time of day, and position of the antenna.
PAGE 26
Si4730/31/34/35-D60 4.14. De-emphasis Pre-emphasis and de-emphasis is a technique used by FM broadcasters to improve the signal-to-noise ratio of FM receivers by reducing the effects of high-frequency interference and noise. When the FM signal is transmitted, a pre-emphasis filter is applied to accentuate the high audio frequencies. The Si473x-D60 incorporates a de-emphasis filter which attenuates high frequencies to restore a flat frequency response. Two time constants are used in various regions.
PAGE 27
Si4730/31/34/35-D60 4.19. Control Interface A serial port slave interface is provided, which allows an external controller to send commands to the Si473xD60 and receive responses from the device. The serial port can operate in two bus modes: 2-wire mode and 3wire mode. The Si473x-D60 selects the bus mode by sampling the state of the GPO1 and GPO2 pins on the rising edge of RST.
PAGE 28
Si4730/31/34/35-D60 Timing Parameters,” on page 10, and Figure 5, “3-Wire Control Interface Read Timing Parameters,” on page 10. 4.20. GPO Outputs The Si473x-D60 provides three general-purpose output pins. The GPO pins can be configured to output a constant low, constant high, or high-impedance. The GPO pins can be reconfigured as specialized functions. 4.21. Firmware Upgrades The Si473x-D60 contains on-chip program RAM to accommodate minor changes to the firmware.
PAGE 29
Si4730/31/34/35-D60 5. Pin Descriptions GPO2/[INT] GPO3/[DCLK] DFS 1 GPO1 NC NC 5.1. Si473x-D60-GM 20 19 18 17 16 FMI 2 15 DOUT RFGND 3 14 LOUT/[DFS] GND PAD AMI 4 13 ROUT/[DOUT] 6 7 8 9 10 SCLK SDIO RCLK VD 12 GND SEN RST 5 11 VA Pin Number(s) Name 1, 20 NC No connect. Leave floating. 2 FMI FM RF inputs. FMI should be connected to the antenna trace. 3 RFGND 4 AMI AM RF input. AMI should be connected to the AM antenna. 5 RST Device reset input (active low).
PAGE 30
Si4730/31/34/35-D60 5.2. Si473x-D60-GU Pin Number(s) Name 1 DOUT 2 3 1 24 LOUT/[DFS] DFS 2 23 ROUT/[DOUT] GPO3/[DCLK] 3 22 DBYP GPO2/[INT] 4 21 VA GPO1 5 20 VD NC 6 19 RCLK NC 7 18 SDIO FMI 8 17 SCLK RFGND 9 16 SEN NC 10 15 RST NC 11 14 GND AMI 12 13 GND Description Digital output data for digital output mode. Digital frame synchronization input for digital output mode.
PAGE 31
Si4730/31/34/35-D60 6.
PAGE 32
Si4730/31/34/35-D60 7. Package Outline 7.1. Si473x-D60 QFN Figure 12 illustrates the package details for the Si473x. Table 15 lists the values for the dimensions shown in the illustration. Figure 12. 20-Pin Quad Flat No-Lead (QFN) Table 15. Package Dimensions Symbol Millimeters Symbol Min Nom Max A 0.50 0.55 0.60 A1 0.00 0.02 0.05 L 0.35 0.40 0.45 b 0.20 0.25 0.30 L1 0.00 — 0.10 c 0.27 0.32 0.37 aaa — — 0.05 bbb — — 0.05 D D2 Min f 3.00 BSC 1.65 2.
PAGE 33
Si4730/31/34/35-D60 7.2. Si473x-D60 SSOP Figure 13 illustrates the package details for the Si473x. Table 16 lists the values for the dimensions shown in the illustration. Figure 13. 24-Pin SSOP Table 16. Package Dimensions Dimension A A1 b c D E E1 e L L2 θ aaa bbb ccc ddd Min — 0.10 0.20 0.10 Nom — — — — 8.65 BSC 6.00 BSC 3.90 BSC 0.635 BSC — 0.25 BSC — 0.20 0.18 0.10 0.10 0.40 0° Max 1.75 0.25 0.30 0.25 1.27 8° Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2.
PAGE 34
Si4730/31/34/35-D60 8. PCB Land Pattern 8.1. Si473x-D60 QFN Figure 14 illustrates the PCB land pattern details for the Si473x-D60-GM QFN. Table 17 lists the values for the dimensions shown in the illustration. Figure 14. PCB Land Pattern 34 Rev. 1.
PAGE 35
Si4730/31/34/35-D60 Table 17. PCB Land Pattern Dimensions Symbol Millimeters Min D D2 Symbol Max 2.71 REF 1.60 1.80 Min Max GE 2.10 — W — 0.34 — e 0.50 BSC X E 2.71 REF Y E2 f GD 1.60 1.80 2.53 BSC 2.10 Millimeters 0.28 0.61 REF ZE — 3.31 ZD — 3.31 — Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on IPC-SM-782 guidelines.
PAGE 36
Si4730/31/34/35-D60 8.2. Si473x-D60 SSOP Figure 15 illustrates the PCB land pattern details for the Si473x-D60-GU SSOP. Table 18 lists the values for the dimensions shown in the illustration. Figure 15. PCB Land Pattern Table 18. PCB Land Pattern Dimensions Dimension Min Max C 5.20 5.30 E 0.635 BSC X 0.30 0.40 Y1 1.50 1.60 General: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This land pattern design is based on the IPC-7351 guidelines. Solder Mask Design: 3.
PAGE 37
Si4730/31/34/35-D60 9. Top Markings 9.1. Si473x-D60 Top Marking (QFN) 3460 DTTT YWW 3160 DTTT YWW 3060 DTTT YWW 3560 DTTT YWW 9.2. Top Marking Explanation (QFN) Mark Method: YAG Laser Line 1 Marking: Part Number 30 = Si4730, 31 = Si4731, 34 = Si4734, 35 = Si4735. Firmware Revision 60 = Firmware Revision 6.0. Die Revision D = Revision D Die. TTT = Internal Code Internal tracking code. Line 2 Marking: Line 3 Marking: Circle = 0.5 mm Diameter Pin 1 Identifier.
PAGE 38
Si4730/31/34/35-D60 9.3. Si473x-D60 Top Marking (SSOP) 473XD60GU YYWWTTTTTT 9.4. Top Marking Explanation (SSOP) Mark Method: Line 1 Marking: Line 2 Marking: 38 YAG Laser Part Number 4730 = Si4730; 4731 = Si4731; 4734 = Si4734; 4735 = Si4735. Die Revision D = Revision D die. Firmware Revision 60 = Firmware Revision 6.0. Package Type GU = 24-pin SSOP Pb-free package YY = Year WW = Work week Assigned by the Assembly House. TTTTTT = Manufacturing code Rev. 1.
PAGE 39
Si4730/31/34/35-D60 10. Additional Reference Resources Contact your local sales representatives for more information or to obtain copies of the following references:       EN55020 Compliance Test Certificate AN332: Si47xx Programming Guide AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines AN388: Si470x/1x/2x/3x/4x Evaluation Board Test Procedure Si47xx EVB User’s Guide Customer Support Site: www.silabs.
PAGE 40
Si4730/31/34/35-D60 DOCUMENT CHANGE LIST Revision 1.0 to Revision 1.1          Updated part number throughout. Updated pin assignments on front page. Updated block diagram on front page. Updated Table 6, “Digital Audio Interface Characteristics,” on page 11. Updated Table 10, “Reference Clock and Crystal Characteristics,” on page 16. Added Table 11, “Thermal Conditions,” on page 16. Updated Section "2. Typical Application Schematic" on page 18. Updated Section "4.
PAGE 41
Si4730/31/34/35-D60 NOTES: Rev. 1.
PAGE 42
Si4730/31/34/35-D60 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: FMinfo@silabs.com Internet: www.silabs.com Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions.