User Manual

COMMUNICATION CERTIFICATION LABORATORY TEST REPORT: 73-6560

FCC ID: NQE1005

air-core inductor. The PLL provides voltage in the range of 0.5V

to 4.0V (measured at TP4) to the varactor for tuning the 1

frequency. The air inductor must be tuned by hand to center the

VCO response for the given voltage input. A control voltage of

0.5 volts corresponds approximately to an output frequency of 960

MHz while a control voltage of 4.0V corresponds approximately

with an output frequency of 990 MHz. The VCO output is buffered

before being sent to the mixer or fed back to the PLL

Chip. The PLL receives a serial control word from one of the

micro controllers to set the synthesizer frequency. The

reference frequency for the PLL is 24 MHz.

FM Demodulator Chip MC13156

The 1

IF of 61.3 MHz enters the FM chip, MC12156, on pin 1,

which is the input to a second mixer. The 2

LO of 72 MHz

enters the mixer on pin 24 of the chip at approximately –3 dBm.

The 2

LO is derived from the third harmonic of the 24 MHz

crystal oscillator that services the PLL and micro controllers.

The output of the mixer is at 10.7 MHz. This 2

IF then passes

through a narrow band ceramic filter, an on chip amplifier,

another ceramic filter, and back on chip to a limiting amplifier.

The filters have 3 dB of loss and a bandwidth of 330kHz; the

amplifiers have 39 dB and 55 dB of gain respectively. The final

stage is a demodulation using an off chip tuned circuit that must

be adjusted for maximum data amplitude and duty cycle symmetry.

The demodulated data signal is then lowpass filtered by an off

chip op-amp circuit before passing onto the microprocessors. The

chip also provides a signal strength indicator on pin 20 in the

form of a current proportional to the signal strength. This

current is converted to a voltage through an adjustable, external

resistor and compared with hysteresis to a set level. The output

of this comparator is called the “squelch” line. The squelch

line goes high (+5V) for signals above the minimum sensitivity of

the receiver and is low (0V) otherwise.

Microprocessors

There are three processors on the receiver. The first one, U5, takes the demodulated data stream

and decodes the Manchester formatting. The decoded data passes along to a processor, U3,

which controls the PLL hopping and performs the verification of the bit stream to determine if it is

valid data. The valid data then passes to U8, which handles interface with the outside world

through the 24-pin motherboard connector.