Data Sheet

SWA54 Module Datasheet Rev 1.2
12
1.9 I2C Master/Slave Communication Interface Timing (S_SCL, S_SDA)
The SWA54 has both I2C slave and master interfaces available with their respective pins S_SCL, S_SDA and
M_SCL, M_SDA. The interfaces operate in I2C fast-mode and can receive and transmit at up to 400 kbit/s.
Bytes are 8 bits long and are transferred with the most significant bit (MSB) first. Each byte has to be followed
by an acknowledge bit. The SWA54 will apply clock-stopping (by holding the clock line S_SCL LOW to force
the master into a wait state) if necessary due to internal high-priority tasks.
The slave/master interface can be used both for writing (e.g. sending commands) or reading (e.g. requesting
status). An additional GPIO pin on the SWA54 (Ex. GPIO24), can be used to notify the I2C master when a
pending message is ready to be sent.
The SWA54 slave interface responds to the 7-bit slave address 1000000 (0x40) as shown in Figure 1 below.
Figure 5: First Byte after the START Procedure
ELECTRICAL SPECIFICATIONS AND TIMING
Table 3: Characteristics of the S_SDA and S_SCL I/Os
PARAMETER SYMBOL
FAST-MODE
UNIT
MIN.
MAX.
LOW level input voltage
VIL
−0.3
0.8
V
HIGH level input voltage
VIH
2.0
3.6
V
LOW level output voltage (open drain or
open collector) at 1 mA sink current:
VOL 0 0.4 V
Output fall time from V
IHmin
to V
ILmax
with
a bus capacitance from 10 pF to 400 pF
tof 0 250 ns
Pulse width of spikes which must be
suppressed by the input filter
tSP 0 50 ns
S_SCL clock frequency
fSCL
0
400
kHz
LOW period of the S_SCL clock
tLOW
1.3
–
µs
HIGH period of the S_SCL clock
tHIGH
0.6
–
µs
Data hold time
tHD;DAT
100
–
ns
Data set-up time
tSU;DAT
100
–
ns