Data Sheet

SWA54 Module Datasheet Rev 1.2
11
Table 2: SWA54 I2S Timing
MIN
TYP
MAX
UNIT
NOTES
V
L
low voltage level
-0.3V
0.0V
0.4V
V
V
H
high voltage level
2.4V
3.3V
3.6V
V
T
clock period
325.5n
s
1/3.072MHz
T
Lo
clock low period
0.4T
0.6T
T
Hi
clock high period
0.4T
0.6T
T
R
rise time
50n
s
Note 1
T
F
fall time
50n
s
Note 1
T
Su
setup time
25n
s
T
Hd
hold time
25n
s
T
Od
output delay
-25n
25n
s
bit clocks/word clock
64
I2S protocol is “I2S Justified” as shown below.
MSB LSB MSB
WORD n-1
RIGHT CHANNEL
WORD n
LEFT CHANNEL
WORD n+1
RIGHT CHANNEL
I2S bit clock
I2S data
I2S word clock
Note 1: The timing specified for the rise and fall times represents the edge rates on the module itself. The rise
and fall times of the I2S signals are determined by ESD/EMI mitigation components on the modules, as well
as external loading, and will be higher than the specified numbers