User's Manual

User manual of 3G SEP EVDO module
Page 40
t(auxsyncd) AUX_PCM_SYNC de-asserted time 62.4 62.5 - us
t(auxclk) AUX_PCM_CLK cycle time - 7.8 - us
t(auxclkh) AUX_PCM_CLK high time 3.8 3.9 - us
t(auxclkl) AUX_PCM_CLK low time 3.8 3.9 - us
t(suauxsync)
AUX_PCM_SYNC setup time to
AUX_PCM_CLK rising
1.95 - - ns
t(hauxsync)
PCM_SYNC hold time after
AUX_PCM_CLK rising
1.95 - - ns
t(suauxdin)
AUX_PCM_DIN setup time to
AUX_PCM_CLK falling
70 - - ns
t(hauxdin)
AUX_PCM_DIN hold time after
AUX_PCM_CLK falling
20 - - ns
t(pauxdout)
Delay from AUX_PCM_CLK to
AUX_PCM_DOUT valid
- - 50 ns
4.14 RF SIGNAL
4.14.1 Load mismatch
The module accepts a VSWR < 20:1 (all phase angles) without damage or
permanent degradation.
The module accepts a VSWR < 12:1 (all phase angles) without any spurious
emission > - 30 dBm.
4.14.2 Input VSWR
The typical input VSWR is 1.5:1 (max = 1.5:1).
4.14.3
Antenna matching network
A matching network in the UMC-3GSEP module is optimized for a 50 ohm
work load.
To obtain the best performance in an application, an additional matching circuit
and adjustment for actual antenna is required. A π-type matching network is
recommended in the UMC-3GSEP Application Note.