User's Manual

User manual of 3G SEP EVDO module
Page 39
t(pdout)
Delay from PCM_CLK rising to
PCM_DOUT valid
- - 60 ns
t(zdout)
Delay from PCM_CLK falling to
PCM_DOUT HIGH-Z
- - 60 ns
4.14.2.2 Auxiliary (long sync) PCM interface (128 kHz clock)
Figure 16: AUX_PCM_SYNC timing
Figure 17: AUX_PCM_CODEC to MDM timing
Figure 18: MDM to AUX_PCM_CODEC timing
Parameter
Condition Min Typ Max Unit
t(auxsync) AUX_PCM_SYNC cycle time - 125 - us
t(auxsynca) AUX_PCM_SYNC asserted time 62.4 62.5 - us