User's Manual

User manual of 3G SEP EVDO module
Page 34
t(mov) Master output data
uncertainty
-5 5 ns
t(mis) Master input setup 0 3 ns
t(moh) Master output hold 0 3 ns
t(tse) Tri-state enable -5 5 ns
t(tsd) Tri-state disable -5 5 ns
Figure 9: SPI in the slave mode
Parameter Comments Minimum Maximum Unit
1/T SPI clock frequency - 26 MHz
t(ch) Clock high 0.45xT 0.55xT ns
t(cl) Clock low 0.45xT 0.55xT ns
t(sov) Slave output data
uncertainty
0 15.8 ns
t(sis) Slave input setup 1.5 - ns
t(sih) Slave input hold 1.5 - ns
4.11 SDIO
Only supports the master mode.