Specifications

GRT1-ML2 timing
PROGRAMMING MANUAL 302
Revision 5.0
A GRT1-ML2 timing
This appendix describes the I/O timing issues for the communication
between the TJ1-MC__, the GRT1-ML2 and the SmartSlice I/O Units. The
information in this section is useful for planning operations that require strict
control of the I/O timing.
In this section, the following is assumed:
• All required slaves participate in the communication.
• The TJ1-MC__ and the GRT-ML2 have no error indications.
• The I/O configuration is properly registered.
• All filter functions in the SmartSlice I/O Units are disabled.
Timing concepts
Refresh cycles
There are two refresh cycles involved in the timing issues:
• The refresh cycle between the TJ1-MC__ and the GRT1-ML2
• The refresh cycle between the GRT1-ML2 and the SmartSlice I/O Units.
Note
To register the I/O configuration, use the REGS dipswitch. See the
Trajexia Hardware Reference Manual.
Note
If the I/O configuration is not properly registered, the system can
operate, but the data exchange is delayed.