Specifications

Wireless-Tag Technology Co., Ltd. V1.0.0
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6
4 Functional Description
4.1 Direct Memory Access Controller (DMA)
The Direct memory access (DMA) is used to provide high-speed data transfer between peripheral and
memory or between memory and memory, without intervention from CPU, data can be transferred quickly
by DMA, which frees up CPU resources for other operations.
The features are as follows:
 Supports 8 independent DMA channels

Each DMA channel has an independent handshake signal
 The priority of each DMA channel is programmable

Each priority arbitration uses a fixed priority determined by the DMA channel number
 Supports various transfer modes

Memory to memory
 Memory to peripheral

Peripheral to memory
 Supports various DMA cycle modes

Supports various DMA transfer data bit width
 Each DMA channel can access the primary and alternate channel controlled data structure

All channel controlled data is stored in system memory in little endian format
 The number of data transferred in a single DMA cycle can be programmed (from 1 to 1024)

The transfer address increment can be greater than the data width
 Can indicate errors on the bus
4.2 Independent Watchdog(IWDG)
The independent watchdog IWDG can be used to detect software and hardware abnormalities, such as the
main clock stops oscillating, the program becomes out of control and no longer refreshes the watchdog.
The features are as follows:
 Free running down counter

Writing to the IWDG_RLR register will reload the watchdog
 After the watchdog is activated, a reset occurs when the counter reaches 0

IWDG interrupt can wake up from sleep mode 0 and sleep mode 2