Specifications
Table Of Contents
- Home
- Table of Contents
- 1 General Information 1-1
- 2 EBC-BX Technical Reference 2-1
- 2.1 Introduction 2-1
- 2.2 Intel FW82443BX / SMSC Victory-66 Chipset 2-1
- 2.3 Memory Installation 2-1
- 2.4 Interrupt Routing 2-2
- 2.5 Power/Reset Connections 2-3
- 2.6 Mouse Interface 2-3
- 2.7 Real Time Clock/Calendar 2-4
- 2.8 Keyboard Interface 2-4
- 2.9 Serial Interface 2-5
- 2.10 Parallel Printer Port 2-12
- 2.11 Speaker/Sound Interface 2-12
- 2.12 PC/104 Bus Interface 2-12
- 2.13 PC/104 Plus Bus Interface 2-13
- 2.14 Floppy Disk Interface 2-14
- 2.15 IDE Hard Disk Interface 2-15
- 2.16 Watchdog Timer Configuration 2-16
- 2.17 Status LED 2-16
- 2.18 Battery Select Control 2-16
- 2.19 DiskOnChip Configuration 2-17
- 2.20 Parallel I/O 2-18
- 2.21 VGA Configuration 2-21
- 2.22 Ethernet Controller 2-23
- 2.23 Fan Power Connector 2-24
- 2.24 Multi I/O Connector 2-25
- 2.25 USB Connector 2-25
- 2.26 Jumper Connector Summary 2-26
- 3 AWARD BIOS Configuration 3-1
- 3.1 General Information 3-1
- 3.2 Entering Setup 3-1
- 3.3 Setup Main Menu 3-1
- 3.4 Standard CMOS Features 3-2
- 3.5 Advanced BIOS Features Setup 3-6
- 3.6 Chipset Features Setup 3-11
- 3.7 Integrated Peripherals Setup 3-14
- 3.8 Power Management Setup 3-19
- 3.9 PNP/PCI Configuration 3-23
- 3.10 PC Health Status 3-25
- 3.11 Frequency/Voltage Control 3-25
- 3.12 Load BIOS Defaults 3-26
- 3.13 Set Supervisor Password 3-27
- 3.14 Set User Password 3-27
- 3.15 Save and Exit Setup 3-27
- 3.16 Exit without Saving 3-27
- 4 EBC-BX DiskOnChip Configuration 4-1
- 5 WS16C48 Programming Reference 5-1
- APPENDIX A I/O Port Map
- APPENDIX B Interrupt Map
- APPENDIX C EBC-BX Parts Placement Guide
- APPENDIX D EBC-BX Parts List
- APPENDIX E EBC-BX Mechanical Drawing
- APPENDIX F WS16C48 I/O Routines and Sample Program Listings
- Warranty and Repair Information

Shad ow ing Op tions
When shad ow ing for a par ticu lar ad dress range is en abled, it in structs the BIOS to copy the BIOS
lo cated in ROM into DRAM. This shad ow ing from an 8- bit EPROM into fast 32- bit DRAM re sults in a
Multi- magnitude in crease in per form ance. The main BIOS is shad owed auto mati cally but there are
other ar eas that may be se lected for shad ow ing as shown here:
Video BIOS Shadow - C000- C7FFF EGA/VGA BIOS ROM
C8000- CBFFF
CC000- CFFFF
D0000- D3FFF
D4000- D7FFF
D8000- DBFFF
DC000- DFFFF
Small Logo(EPA) Show
This op tion when en abled in structs the BIOS to dis play the EPA Energy- Star logo in the up per right
cor ner of the screen dur ing the POST pro cess.
3.6 Chipset Fea tures Setup
The op tions in this sec tion con trol the chipset pro gram ming at boot time. In most cases, the de fault
set tings should be used un less you have a clear un der stand ing of the sig nifi cance of the change. It is pos -
si ble us ing these op tions to cre ate a sys tem that will ei ther not boot or is very un sta ble or un re li able. If
this should oc cur, there are two meth ods to re turn the sys tem to a sta ble con figu ra tion. If the sys tem
works well enough to get into Setup, sim ply choose the “Load BIOS De faults” op tion and then se l ect
“Save and Exit Setup” to re store fac tory de faults. If the sys tem will not run well enough to run Setup, it
will be nec es sary to re move the bat tery source tem po rar ily un til the CMOS mem ory de cays. Ref er to
Sec tion 2.7 for de tails on re ini tial iz ing the CMOS RAM.
Each of the op tions for the Chipset Fea tures Menu will be briefly dis cussed in the sections that fol -
low.
SDRAM RAS- to- CAS De lay
This op tion al lows for se lec tion of the number of clock to de lay the RAS to CAS tran si tion. The
avail able choices are :
3 Clocks
2 Clocks
030923 OPERATIONS MANUAL EBC-BX Page 3 - 11
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