Specifications
Table Of Contents
- Home
- Table of Contents
- 1 General Information 1-1
- 2 EBC-BX Technical Reference 2-1
- 2.1 Introduction 2-1
- 2.2 Intel FW82443BX / SMSC Victory-66 Chipset 2-1
- 2.3 Memory Installation 2-1
- 2.4 Interrupt Routing 2-2
- 2.5 Power/Reset Connections 2-3
- 2.6 Mouse Interface 2-3
- 2.7 Real Time Clock/Calendar 2-4
- 2.8 Keyboard Interface 2-4
- 2.9 Serial Interface 2-5
- 2.10 Parallel Printer Port 2-12
- 2.11 Speaker/Sound Interface 2-12
- 2.12 PC/104 Bus Interface 2-12
- 2.13 PC/104 Plus Bus Interface 2-13
- 2.14 Floppy Disk Interface 2-14
- 2.15 IDE Hard Disk Interface 2-15
- 2.16 Watchdog Timer Configuration 2-16
- 2.17 Status LED 2-16
- 2.18 Battery Select Control 2-16
- 2.19 DiskOnChip Configuration 2-17
- 2.20 Parallel I/O 2-18
- 2.21 VGA Configuration 2-21
- 2.22 Ethernet Controller 2-23
- 2.23 Fan Power Connector 2-24
- 2.24 Multi I/O Connector 2-25
- 2.25 USB Connector 2-25
- 2.26 Jumper Connector Summary 2-26
- 3 AWARD BIOS Configuration 3-1
- 3.1 General Information 3-1
- 3.2 Entering Setup 3-1
- 3.3 Setup Main Menu 3-1
- 3.4 Standard CMOS Features 3-2
- 3.5 Advanced BIOS Features Setup 3-6
- 3.6 Chipset Features Setup 3-11
- 3.7 Integrated Peripherals Setup 3-14
- 3.8 Power Management Setup 3-19
- 3.9 PNP/PCI Configuration 3-23
- 3.10 PC Health Status 3-25
- 3.11 Frequency/Voltage Control 3-25
- 3.12 Load BIOS Defaults 3-26
- 3.13 Set Supervisor Password 3-27
- 3.14 Set User Password 3-27
- 3.15 Save and Exit Setup 3-27
- 3.16 Exit without Saving 3-27
- 4 EBC-BX DiskOnChip Configuration 4-1
- 5 WS16C48 Programming Reference 5-1
- APPENDIX A I/O Port Map
- APPENDIX B Interrupt Map
- APPENDIX C EBC-BX Parts Placement Guide
- APPENDIX D EBC-BX Parts List
- APPENDIX E EBC-BX Mechanical Drawing
- APPENDIX F WS16C48 I/O Routines and Sample Program Listings
- Warranty and Repair Information
2.20 Par al lel I/O
The EBC- BX util izes the Win Sys tems WS16C48 ASIC high- density I/O chip mapped at a base ad -
dress of 120H. The first 24 lines are ca pa ble of fully latched event sens ing with sense po lar i ty be ing
soft ware pro gram ma ble. Two, 50- pin con nec tors al low for easy mat ing with in dus try stan d ard I/O
racks. The pin out for the two con nec tors are shown on the next page.
2.20.1 Par al lel I/O En able
The par al lel fea tures of the EBC- BX can be en abled or dis abled us ing the jumper block at J6. When
J6 is jumpered the par al lel I/O is en abled at I/O ad dress 120H. When J6 is open the 16 ad dresses start ing
at I/O ad dress 120H are free for use by other de vices.
2.20.2 Par al lel I/O VCC En able
The I/O con nec tors can pro vide +5 volts to an I/O rack or for mis cel la ne ous pur poses by jump er ing
J14. When J14 is jumpered +5 volts is pro vided at pin 49 of both J7 and J9. It the user's re spon si bil ity to
limit cur rent to a safe value (less than 400mA ) to avoid dam ag ing the CPU board.
2.20.3 Par al lel I/O Con nec tors
The 48 lines of par al lel I/O are ter mi nated through two 50- pin con nec tors at J7 and J9. The J7 con -
nec tor han dles I/O ports 0-2 while J9 han dles ports 3-5. The pin defi ni tions for J7 and J9 are shown on
the fol low ing page.
Page 2 - 18 OPERATIONS MANUAL EBC-BX 030923
WinSystems - "The Embedded Systems Authority"
2 1
o o
J6
2 1
o o
J14
J6 Par al lel I/O En able
J14 Par al lel I/O +5V Supply Enable