Specifications

2.9.2 RS- 485 Mode Con figu ra tion
The RS- 485 Multi- drop in ter face is sup ported on both chan nels with the in stal la tion of the op tional
“Chip Kit”, Win Sys tems’ part number CK- 75176-2. A sin gle kit is suf fi cient to con fig ure both chan -
nels for RS- 485. RS- 485 is a 2- wire multi- drop in ter face where only one sta tion at a time talks (trans -
mits) while all oth ers lis ten (re ceive). RS- 485 usu ally re quires the twisted pair be ter mi n ated at each end
of the run. The re quired ter mi na tion val ues are de pend ent upon a number of fac tors in clud ing: line im -
ped ance, line length, etc. A good trial value is 100 ohms in all three re sis tor lo ca tions. The fol low ing il -
lus tra tions show the cor rect jump er ing, driver IC in stal la tion, I/O con nec tor pin out, and ter mi na tion
re sis tor lo ca tions for each of the chan nels when used in RS- 485 mode.
COM1 - RS- 485
Im por tant Note: All se rial ter mi na tion com po nents are sur face mount 0805 pack ages on the
bot tom of the board. These should only be in stalled by sur face mount quali fied in di vidu als.
030923 OPERATIONS MANUAL EBC-BX Page 2 - 9
3 2 1
o o o
1 2 3
o o o
U4 - Not In stalled
U9 - In stalled
U5 - Not In stalled
1 o o 6
2 o o 7
3 o o 8
4 o o 9
5 o
J15 J17
COM1 DB9
N/C
TX/RX+
TX/RX-
N/C
GND
N/C
N/C
N/C
N/C
VCC
TX/RX+
TX/RX-
R108
R106
R109
RS- 485 NOTE : Be cause RS- 485 uses a sin gle
twisted- pair, all trans mit ters are con nected in par al -
lel. Only one sta tion at a time may trans mit or have
its trans mit ter en abled. The trans mit ter En able/Dis -
able is con trolled in soft ware us ing bit 1 in the Mo -
dem Con trol Reg is ter (RTS). When RTS is set, the
trans mit ter is en abled, and when cleared (the nor mal
state) the trans mit ter is dis abled and the re ceiver is
en abled. Note that it is nec es sary to al low some
mini mal set tling time af ter ena bling the trans mit ter
bef ore trans mit ting the first char ac ter. Like wise, fol -
low ing a trans mis sion, it is nec es sary to be sure that
all char ac ters have been com pletely shifted out of
the UART (Check Bit 6 in the Line Status Reg is ter)
bef ore dis abling the trans mit ter to avoid chop ping
off the last char ac ter.