Data Sheet

iTM1011-C DataSheet
Proprietary & Confidential Information ioTTech Corporation, Taiwan
Doc. NO:
11
6. Host Interface Timing Diagram
6.1 Power UP Sequence
Shows the below figure, the power-on sequence of the iTM1011-C from power-up to
firmware download, including the initial device power-on reset evoked by LDO_EN signal.
After initial power-on, the LDO_EN signal can be held low to turn off the iTM1011-C.
After LDO_EN is assert and host starts the power-on sequence of the iTM1011-C. From that
point, the typical power-on sequence is shown below:
1. Within 1.3 millisecond, the internal power-on reset (POR) will be done. And host could
download firmware code of DPLL setting if the internal running clock is crystal frequency.
2. After 100us of DPLL settling time, host could set internal clock to full speed and finish all
the downloading of firmware code.