User manual

BIOS Setup
54
POST
Code
(Hex)
Name Description
17h
PRE_SIZE_RAM
Initialize external cache before autosizing
memory.
18h
TIMER_INIT
Initialize all three of the 8254 timers.
1Ah
DMA_INIT
Initialize the DMA command register and
all 8 DMA channels.
1Ch
RESET_PIC
Initialize the 8259 interrupt controller.
20h
REFRESH
Copy test code to RAM and execute that
code looking for refresh bit in port 61h to
toggle.
IF <refresh test failed> THEN
Halt.
ENDIF
22h
8742_TEST
Read 8742 self-test results.
IF <self-test failed> THEN
Halt.
ELSE
Read system info from 8742
Set 8742 command byte.
ENDIF
24h
SET_HUGE_ES
Go into protected mode.
Set ES, DS, SS, FS, and GS to 4Gb.
28h
SIZE_RAM
Determine the size of each DRAM bank.
Set DRAM controller configuration
registers to enable DRAM.
29h
MEM_MGR_INIT
Initialize the POST Memory manager.
2Ah
ZERO_BASE_RA
M
Clear the 512k of DRAM.
2Ch
ADDR_TEST
Test for stuck address line in lower 1M of
address space,
IF <test failed> THEN
Halt.
ENDIF
2Eh
BASERAML
Test for stuck DRAM data line by walking
a 1 throug all bit locations of address 0
and then walking a 0 through.
IF <test failed> THEN
Halt.
ENDIF
2Fh
PRE_SYS_SHAD
OW
Clears the cache before shadowing the
system.
32h
COMPUTE_SPEE
D
Determine the CPU core speed by timing
the execution of a loop.